Cache Miss Counts from RISC V simulator

[Pavitra Bhade]

Hi all,

I am interested in running my code on a RISC V simulator (as I do not have any hardware), and also find the number of cache misses for the code execution. Which simulator would allow me the same?

Regards,

Pavitra Prakash Bhade

IIT Goa

[Tommy Murphy]

Cache architecture is really going to be very target/implementation specific rather than a generic RISC-V characteristic. For example, different systems may implement some or all of L1/L2/L3 instruction and/or data caches of different sizes. I doubt that any existing RISC-V simulator is going to have the capabilities to model an arbitrary cache configuration. You probably need to be more specific about the type of system and cache configuration that you're intending to target/test against.

[John Leidel]

We actually have a reasonably accurate RISC-V model built using
Sandia's SST PDES infrastructure. It's open source and will soon
support the existing SST "memHierarchy". This will provide arbitrary
cache configs as well as a myriad of potential memory backends (DRAM,
HBM, Flash, etc). Our model is a work in progress, but feel free to
take a look:

https://github.com/tactcomplabs/rev

On Tue, Aug 2, 2022 at 6:36 PM Tommy Murphy <tommy_...@hotmail.com> wrote:
>
> Cache architecture is really going to be very target/implementation specific rather than a generic RISC-V characteristic. For example, different systems may implement some or all of L1/L2/L3 instruction and/or data caches of different sizes. I doubt that any existing RISC-V simulator is going to have the capabilities to model an arbitrary cache configuration. You probably need to be more specific about the type of system and cache configuration that you're intending to target/test against.
>

> --
> You received this message because you are subscribed to the Google Groups "RISC-V SW Dev" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+un...@groups.riscv.org.
> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/LO2P265MB4776BAC2855BA448C0A783DBF99D9%40LO2P265MB4776.GBRP265.PROD.OUTLOOK.COM.

[Tommy Murphy]

Thanks John, that's very interesting.

Just one point on this:

https://github.com/tactcomplabs/rev#building-compatible-compilers

Shouldn't users be building the RISC-V gcc tools from the upstream gcc etc. repositories rather than riscv-gnu-toolchain these days?

Also, presumably cache profiling results vary depending on the tools used - e.g. gcc, llvm, commercial etc.?

[John Leidel]

Tommy, that's part of what we're working on updating (the toolchain
section). Lots of work going into Rev very soon. But you are
correct.

The profiling results will be based upon the cache configuration
options within SST memHierarchy. Its a cycle approximate model with a
variety of knobs to tune. The tools used to build the application
will certainly steer the application code in one direction or another
(which will ultimately affect cache performance). Is that what you're
referring to?

best
john

[Pavitra Bhade]

I somehow want to use a Risc v simulator to run my codes and give me performance counter values like cache miss counts. I need this for the purpose of attack detection methods. Which simulator will help new achieve that? 

[Daniel Petrisko]

Hi Pavitra,

Have you considered gem5? Pretty standard research tool for these kinds of uarch simulations  (https://www.gem5.org)

Best,

Dan

On Aug 2, 2022, at 6:10 PM, Pavitra Bhade <pavi...@gmail.com> wrote:



--

You received this message because you are subscribed to the Google Groups "RISC-V SW Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+un...@groups.riscv.org.

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/CABFsR%2BM7pMKkGBwQxTs3D8i6NafnqkVoN90_0Cb-XHXk-_6pUw%40mail.gmail.com.

[Pavitra Bhade]

Yes sir I heard its a good approach to go with gem 5 for such microarchitectural simulations. But will it help me get the performance counters? 

[钟乘永]

Hi Pavitra,

Yeah, Gem5 will output statistic for every simulation, which contains cache miss, branch predictor mispredict, etc.

 Feel free to try it.

BR,

Zhong

Pavitra Bhade <pavi...@gmail.com> 于2022年8月3日周三 10:24写道：

To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/CABFsR%2BNKYPZV%3DFbcTtpRmBts0HKs7m6WA%2BE8TMC0jP5i5CtF0Q%40mail.gmail.com.

[Pavitra Bhade]

Is there any existing RISC V repository of Gem5? Or should i build it? Also is it multicore?

[Pavitra Bhade]

Thank you for your suggestion sir. I will definitely try gem5. Another quick question, will I be able to get any other simulators in RISC V processors? Because I am currently working on the Comet processor developed by INRIA. However its inorder uni-core processor. Hence for detection of speculative based attacks, i wanted to try my method on another processor, like the BOOM etc. Are there simulators for such processors available?

[chengyong zhong]

Yep, Gem5 repository:https://gem5.googlesource.com/public/gem5 or search it on github.

Following the user manual to build gem5 and run.

Yes, multicore is supported.

Pavitra Bhade <pavi...@gmail.com> 于2022年8月3日周三 14:44写道：

[chengyong zhong]

Maybe spike is suitable for you if you just care about functional correctness. https://github.com/riscv-software-src/riscv-isa-sim

Pavitra Bhade <pavi...@gmail.com> 于2022年8月3日周三 14:46写道：

[Tommy Murphy]

> Tommy, that's part of what we're working on updating (the toolchain

> section).  Lots of work going into Rev very soon.  But you are
correct.

Fair enough. :-)

> The tools used to build the application
> will certainly steer the application code in one direction or another
> (which will ultimately affect cache performance).  Is that what you're
> referring to?

Sorry, that was more of a general question/comment about the possible impact of the tools used on the cache profiling on general, and not specifically about the rev model for SST. Apologies for the confusion.

[Rishiyur Nikhil]

>    Maybe spike is suitable for you if you just care about functional correctness

I believe Pavitra is looking for performance data (cache miss counts etc.), i.e., beyond functional correctness. Spike will not be suitable for that.

Also, Pavitra, note that Gem is open source and customizable;  research groups frequently modify Gem (a) for new processor microarchitectures and (b) to measure exactly what they may need for their research.  Many, many papers in the major architecture conferences (ISCA, ASPLOS, ...) are based on results obtained in this way.

Nikhil