RISC-V hardware page table walker and Virtual Memory

[Suseela Budi]

Few questions related to virtual memory.

Is RISCV expects hardware page table walker? What is the strategy?

What about no. of bits for virtual and physical page number?

[David Chisnall]

On 4 Jan 2017, at 09:59, Suseela Budi <bsl.rg...@gmail.com> wrote:
>
> Is RISCV expects hardware page table walker? What is the strategy?

From the perspective of the software, it is as if such a thing exists. From the perspective of hardware implementors, it is sufficient to deliver a trap to firmware that will then fill in the TLB entry. This is likely to be a common choice for simple in-order chips, as hardware page-table walkers are primarily useful in designs that do a lot of speculative execution (as TLB misses don’t have to block speculation).

> What about no. of bits for virtual and physical page number?

These are all documented in the privileged spec.

David

[Suseela Budi]

Is it means TLB miss (TLB filling) is done by OS or software?

What about page table management?
What all things are done by software?

[Samuel Falvo II]

On Wed, Jan 4, 2017 at 6:53 AM, Suseela Budi <bsl.rg...@gmail.com> wrote:
> Is it means TLB miss (TLB filling) is done by OS or software?

Not specified by the RISC-V specifications. This is CPU dependent.

> What about page table management?

Not specified by the RISC-V specifications. This is OS dependent.

> What all things are done by software?

Not specified by the RISC-V specifications.

Remember that RISC-V is a *family* of instruction set specifications.
They are not *implementations*. It's entirely up to the implementer
of the processor to provide answers to these questions. You should
consult the documentation of your specific processor for more details;
if it's your own processor, you're free to decide how to do these
things yourself. :)

You can even implement a RISC-V "processor" by completely emulating
the whole thing in software if you wanted to, similar to how Transmeta
CPUs implemented an 80x86-compatible processor using VLIW technology
years ago. The specifications hosted on risc-v.org doesn't care.

The ISA (user and privilege mode alike) specifications exist to
provide an *interface* between your software and whatever is actually
running it.

--
Samuel A. Falvo II

[Suseela Budi]

Sorry, I mean to say for Linux OS on RISC-V hardware.

Do the current Linux, supports software TLB filling and page table walker?

Is CPU dependent means hardware support?