RISC-V Compiler Explorer (riscv32, riscv64, x86-32 and x86-64)

435 views
Skip to first unread message

Michael Clark

unread,
Jul 25, 2017, 11:44:42 PM7/25/17
to RISC-V SW Dev
Hi,

Let me know if this link works and if the performance is usable:

- https://cx.rv8.io/g/AnaUnz

I’ve set up Matt Godbolt’s compiler-explorer on a Google Cloud f1.micro instance.

The instance has an experimental musl-riscv gcc 7.1.0 toolchain for riscv32, riscv64, x86-32 and x86-64

- https://github.com/rv8-io/musl-riscv-toolchain/releases/tag/v7.1.0-2

We can use it in the meantime until Matt sets up some riscv toolchains (newlib, gcc) on godbolt.org.

Michael.

Bruce Hoult

unread,
Jul 26, 2017, 7:05:55 AM7/26/17
to Michael Clark, RISC-V SW Dev
I'm sure the speed is fine.

Can it show machine code hex, and have different -march options?


Michael.

--
You received this message because you are subscribed to the Google Groups "RISC-V SW Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+unsubscribe@groups.riscv.org.
To post to this group, send email to sw-...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/sw-dev/.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/DC802907-44E8-4E30-9326-1CF4C1A0CF5F%40mac.com.

Michael Clark

unread,
Jul 26, 2017, 8:32:08 AM7/26/17
to Bruce Hoult, RISC-V SW Dev
Hi Bruce,

You can add -march options in the compiler switches command line area at the top right of each compiler window.

I'm not sure about how to configure compiler-explorer to show instruction words in the output. There is a global config option for objdump which I've not set. I have a feeling from looking at the config examples that I might need to point it at a shell script that does file and invokes the architecture specific objdump as it is a global. Matt's AWS example config points at a special objdump.

The default config btw is to just locate the compilers on the host machine. I had to look at some of Matt's AWS config examples to figure out how to get it working with multiple architectures. e.g. using the compiler group feature.

It also requires a google API key to get the URL shortener to work which took me a while to figure out as that is also off by default. I had to enable the API and configure an API key in the Google Developer console.

There is also an LD_PRELOAD compiler wrapper that is off by default which is likely there to harden the setup for the cloud. I thought I switched on that option.

It was quite easy to set up. I guess adding ARM32 and ARM64 might be possible... it took ages to upload the toolchain and the machine is too meagre to actually build a toolchain.

It would be kinda nice to have on the riscv.org domain although it likely needs to be sandboxed from other apps. The only thing I have on that box is an SSL proxy to enable https on GitHub pages (as GitHub don't seem to have letsencrypt configured if you use a custom domain for GitHub pages). I reused the apache https proxy config as by default node binds to an ephemeral port serving http. Secure compiler snippets. :-D

Michael

Sent from my iPhone

Bruce Hoult

unread,
Jul 26, 2017, 12:10:36 PM7/26/17
to Michael Clark, RISC-V SW Dev
> It was quite easy to set up. I guess adding ARM32 and ARM64 might be
> possible... it took ages to upload the toolchain and the machine is too
> meagre to actually build a toolchain.

Once you have your AWS disk images, it's easy enough to crank up a c4.8xlarge spot instance for about 40c/hour (36 threads, 60 GB RAM) using the same disk images (or temporary ones and scp the results across)


To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+un...@groups.riscv.org.

--
You received this message because you are subscribed to the Google Groups "RISC-V SW Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+unsubscribe@groups.riscv.org.
To post to this group, send email to sw-...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/sw-dev/.
Reply all
Reply to author
Forward
0 new messages