Public review for Non-ISA Specification: psABI

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Kito Cheng

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Jul 14, 2022, 12:10:44 PMJul 14
to RISC-V SW Dev (sw-dev@groups.riscv.org), RISC-V ISA Dev
We are delighted to announce the start of the public review period for psABI.

The review period begins today, 2022/07/14, and ends on 2022/08/29 (inclusive).

This Non-ISA specification is described in the PDF available at:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc3


which was generated from the source available in the following GitHub repo:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc


To respond to the public review, please either email comments to the
public isa-dev (isa...@groups.riscv.org) mailing list or add issues
and/or pull requests (PRs) to the GitHub repo
(https://github.com/riscv-non-isa/riscv-elf-psabi-doc). We welcome all
input and appreciate your time and effort in helping us by reviewing
the specification.


During the public review period, corrections, comments, and
suggestions, will be gathered for review by the psABI Task Group. Any
minor corrections and/or uncontroversial changes will be incorporated
into the specification. Any remaining issues or proposed changes will
be addressed in the public review summary report. If there are no
issues that require incompatible changes to the public review
specification, the psABI Task Group will recommend the updated
specifications be approved and ratified by the RISC-V Technical
Steering Committee and the RISC-V Board of Directors.


Thanks to all the contributors for all their hard work.

Kito Cheng

Liviu Ionescu

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Jul 14, 2022, 12:21:36 PMJul 14
to Kito Cheng, RISC-V SW Dev (sw-dev@groups.riscv.org), RISC-V ISA Dev


> On 14 Jul 2022, at 19:10, Kito Cheng <kito....@sifive.com> wrote:
>
> ... To respond to the public review, please either email comments to the
> public isa-dev

I did not follow the recent developments, was the idea to have a RISC-V EABI discarded? Since there is no reference to it in the mentioned document.

Regards,

Liviu

Jim Wilson

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Jul 14, 2022, 5:41:33 PMJul 14
to Liviu Ionescu, Kito Cheng, RISC-V SW Dev (sw-dev@groups.riscv.org), RISC-V ISA Dev
On Thu, Jul 14, 2022 at 9:21 AM Liviu Ionescu <i...@livius.net> wrote:
I did not follow the recent developments, was the idea to have a RISC-V EABI discarded? Since there is no reference to it in the mentioned document.

There was no agreement on what the EABI should be, and not enough time and manpower to create a consensus.  So it was deferred indefinitely.

Jim
 

Bruce Hoult

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Jul 14, 2022, 8:13:02 PMJul 14
to Jim Wilson, Liviu Ionescu, Kito Cheng, RISC-V SW Dev (sw-dev@groups.riscv.org), RISC-V ISA Dev
People who want an EABI want it to decrease interrupt latency -- generally I think in a "it's better if you can match ARMv7-M" thinking. I get the impression there was some shock at how much having fewer A and T registers slowed down code such as Embench. Also __attribute__((interrupt)) solves any latency problem in most cases, with even lower latency than ARMv7-M because the code only saves registers it absolutely needs to.

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Jim Wilson

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Jul 14, 2022, 9:16:38 PMJul 14
to Bruce Hoult, Liviu Ionescu, Kito Cheng, RISC-V SW Dev (sw-dev@groups.riscv.org), RISC-V ISA Dev
On Thu, Jul 14, 2022 at 5:12 PM Bruce Hoult <br...@hoult.org> wrote:
People who want an EABI want it to decrease interrupt latency -- generally I think in a "it's better if you can match ARMv7-M" thinking. I get the impression there was some shock at how much having fewer A and T registers slowed down code such as Embench. Also __attribute__((interrupt)) solves any latency problem in most cases, with even lower latency than ARMv7-M because the code only saves registers it absolutely needs to.

There was no agreement on how to reduce interrupt latency, or whether we even needed to reduce interrupt latency.  One contributor wanted to reduce the number of temp and arg registers.  One contributor wanted to keep the ABI unchanged and determine what registers to save at link time by using register usage info saved in object files.  Attribute interrupt works well for leaf functions.  But if your interrupt function calls another function, then the compiler needs to save a lot of registers unless you change the ABI, or else you use link time optimization to determine the exact set of registers that need to be saved across the function call.

Anyways, as I said, there was no consensus on anything, and not enough time or manpower to create a consensus.  This really should be a separate discussion.

Jim

Liviu Ionescu

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Jul 15, 2022, 1:44:53 AMJul 15
to Jim Wilson, Kito Cheng, RISC-V SW Dev (sw-dev@groups.riscv.org), RISC-V ISA Dev
Ok, I read it as "there was no interest in a RISC-V microcontroller profile, so focus was kept on Unix class devices".

No problem, Arm covers the microcontroller space just fine.

Liviu

Bruce Hoult

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Jul 15, 2022, 4:16:12 AMJul 15
to Liviu Ionescu, Jim Wilson, Kito Cheng, RISC-V SW Dev (sw-dev@groups.riscv.org), RISC-V ISA Dev
So , apparently, does RISC-V, as those 10 billion cores shipped aren't in laptops or phones.


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Tommy Murphy

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Jul 15, 2022, 5:59:45 AMJul 15
to Bruce Hoult, Liviu Ionescu, Jim Wilson, Kito Cheng, RISC-V SW Dev (sw-dev@groups.riscv.org), RISC-V ISA Dev
> So , apparently, does RISC-V, as those 10 billion cores shipped aren't in laptops or phones.

*Claimed* to have been shipped?
I've seen zero independent verification of that figure and industry watchers have also struggled to find any.

Andrew Waterman

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Jul 15, 2022, 6:16:12 AMJul 15
to Tommy Murphy, Bruce Hoult, Jim Wilson, Kito Cheng, Liviu Ionescu, RISC-V ISA Dev, RISC-V SW Dev (sw-dev@groups.riscv.org)
Folks, chill. Liviu was just letting off some steam; we do care about and will eventually have an EABI; and this thread need not digress any further.

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