The state of 32-bit build tools

[Tommy Thorn]

The default build of the riscv-tools works great for producing runnable 64-bit executables. The state of 32-bit is a different matter. While this has been
discussed in the past, I’m not sure what the current status is and where
it’s going.

From my experience:

0. riscv-tools master branch (pt 419f1b5) when built with vanilla build.sh
cannot produce 32-bit executables as multilibs aren’t supported.

Are there any plans to change that?

1. The riscv-tools can be built for 32-bit. I was successful with this
less elegant approach:

$ . build.common
$ build_project riscv-gnu-toolchain --prefix=$RISCV --with-xlen=32

However, this seems poorly supported:
- spike doesn’t find pk
- and even with an explicit path and a -m2048 argument, the binary
isn’t working.

What am I missing?

Thanks
Tommy

[Christopher Celio]

1. The riscv-tools can be built for 32-bit.  I was successful with this
 less elegant approach:

 $ . build.common
 $ build_project riscv-gnu-toolchain --prefix=$RISCV --with-xlen=32

However, this seems poorly supported:
- spike doesn’t find pk
- and even with an explicit path and a -m2048 argument, the binary
  isn’t working.

Did you also build a 32-bit pk? 

Spike is looking for the pk at a relative path (e.g., $RISCV/riscv64-unknown-elf/bin/pk), and isn't finding your pk. First, you need to build your pk using your 32-bit RISC-V gcc (so it should be in riscv32-unknown-elf/bin I think), and then you need to make Spike understand where that is. 

Actually, it's the riscv-fesvr that is in charge of finding where the binaries are that are passed to spike as arguments. It first looks in "TARGET_DIR", which is based on TARGET_ARCH, which is default riscv64-unknown-elf.  I have no idea how to make riscv-fesvr look in riscv32-unknown-elf, other than the obvious hack of setting that bash environment variable when you build it.

The other option is to manually specify the full path to your 32-bit pk. But you said that's not working? Did you verify your pk is 32-bits?

-Chris

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[Tommy Thorn]

Hi Chris,

Did you also build a 32-bit pk? 

I built it with

  CC= CXX= build_project riscv-pk --prefix=$RISCV/riscv32-unknown-elf --host=riscv32-unknown-elf

and file claims it’s a 32-bit ELF.  (Besides it was built with the 32-bit-only toolchain, so I’m pretty confident).

Spike is looking for the pk at a relative path (e.g., $RISCV/riscv64-unknown-elf/bin/pk), and isn't finding your pk. First, you need to build your pk using your 32-bit RISC-V gcc (so it should be in riscv32-unknown-elf/bin I think), and then you need to make Spike understand where that is. 

I know.  I was trying to point that out and I did provide an absolute path.

The other option is to manually specify the full path to your 32-bit pk. But you said that's not working? Did you verify your pk is 32-bits?

tommy@whitebox:~$ which spike

/home/tommy/rv-build/dist32/bin/spike

tommy@whitebox:~$ file rv-build/dist32/riscv32-unknown-elf/bin/pk

rv-build/dist32/riscv32-unknown-elf/bin/pk: ELF 32-bit LSB executable, UCB RISC-V, version 1 (SYSV), statically linked, not stripped

tommy@whitebox:~$ file hw.32

hw.32: ELF 32-bit LSB executable, UCB RISC-V, version 1 (SYSV), statically linked, not stripped

tommy@whitebox:~$ spike -m2048 -l rv-build/dist32/riscv32-unknown-elf/bin/pk hw.32

core   0: 0x0000000000000200 (0x00000093) li      ra, 0

core   0: 0x0000000000000204 (0x00000113) li      sp, 0

…

core   0: 0x0000000000002d60 (0x344176f3) csrrci  a3, mip, 2

core   0: 0x0000000000002d64 (0x0330000f) fence

core   0: 0x0000000000002d68 (0xfd872703) lw      a4, -40(a4)

core   0: 0x0000000000002d6c (0xf20704e3) beqz    a4, pc - 216

core   0: 0x0000000000002c94 (0x02f42423) sw      a5, 40(s0)

core   0: 0x0000000000002c98 (0x341027f3) csrr    a5, mepc

core   0: 0x0000000000002c9c (0x00478793) addi    a5, a5, 4

core   0: 0x0000000000002ca0 (0x34179073) csrw    mepc, a5

core   0: 0x0000000000002ca4 (0x00c12083) lw      ra, 12(sp)

core   0: 0x0000000000002ca8 (0x00000513) li      a0, 0

core   0: 0x0000000000002cac (0x00812403) lw      s0, 8(sp)

core   0: 0x0000000000002cb0 (0x01010113) addi    sp, sp, 16

core   0: 0x0000000000002cb4 (0x00008067) ret

core   0: 0x00000000000003c0 (0x00412083) lw      ra, 4(sp)

core   0: 0x00000000000003c4 (0x00c12183) lw      gp, 12(sp)

core   0: 0x00000000000003c8 (0x01012203) lw      tp, 16(sp)

core   0: 0x00000000000003cc (0x01412283) lw      t0, 20(sp)

core   0: 0x00000000000003d0 (0x01812303) lw      t1, 24(sp)

core   0: 0x00000000000003d4 (0x01c12383) lw      t2, 28(sp)

core   0: 0x00000000000003d8 (0x02012403) lw      s0, 32(sp)

core   0: 0x00000000000003dc (0x02412483) lw      s1, 36(sp)

core   0: 0x00000000000003e0 (0x02c12583) lw      a1, 44(sp)

core   0: 0x00000000000003e4 (0x03012603) lw      a2, 48(sp)

core   0: 0x00000000000003e8 (0x03412683) lw      a3, 52(sp)

core   0: 0x00000000000003ec (0x03812703) lw      a4, 56(sp)

core   0: 0x00000000000003f0 (0x03c12783) lw      a5, 60(sp)

core   0: 0x00000000000003f4 (0x04012803) lw      a6, 64(sp)

core   0: 0x00000000000003f8 (0x04412883) lw      a7, 68(sp)

core   0: 0x00000000000003fc (0x04812903) lw      s2, 72(sp)

core   0: 0x0000000000000400 (0x04c12983) lw      s3, 76(sp)

core   0: 0x0000000000000404 (0x05012a03) lw      s4, 80(sp)

core   0: 0x0000000000000408 (0x05412a83) lw      s5, 84(sp)

core   0: 0x000000000000040c (0x05812b03) lw      s6, 88(sp)

core   0: 0x0000000000000410 (0x05c12b83) lw      s7, 92(sp)

core   0: 0x0000000000000414 (0x06012c03) lw      s8, 96(sp)

core   0: 0x0000000000000418 (0x06412c83) lw      s9, 100(sp)

core   0: 0x000000000000041c (0x06812d03) lw      s10, 104(sp)

core   0: 0x0000000000000420 (0x06c12d83) lw      s11, 108(sp)

core   0: 0x0000000000000424 (0x07012e03) lw      t3, 112(sp)

core   0: 0x0000000000000428 (0x07412e83) lw      t4, 116(sp)

core   0: 0x000000000000042c (0x07812f03) lw      t5, 120(sp)

core   0: 0x0000000000000430 (0x07c12f83) lw      t6, 124(sp)

core   0: 0x0000000000000434 (0x00051863) bnez    a0, pc + 16

core   0: 0x0000000000000438 (0x02812503) lw      a0, 40(sp)

core   0: 0x000000000000043c (0x00812103) lw      sp, 8(sp)

core   0: 0x0000000000000440 (0x10000073) sret

core   0: 0x000000000000c8bc (0x00008067) ret

core   0: 0x00000000000009ec (0xfe050ce3) beqz    a0, pc - 8

core   0: 0x00000000000009f0 (0x02a41063) bne     s0, a0, pc + 32

core   0: 0x00000000000009f4 (0x0330000f) fence

core   0: 0x00000000000009f8 (0x01c12083) lw      ra, 28(sp)

core   0: 0x00000000000009fc (0x00812503) lw      a0, 8(sp)

core   0: 0x0000000000000a00 (0x00000593) li      a1, 0

core   0: 0x0000000000000a04 (0x01812403) lw      s0, 24(sp)

core   0: 0x0000000000000a08 (0x02010113) addi    sp, sp, 32

core   0: 0x0000000000000a0c (0x00008067) ret

core   0: 0x0000000000000ae0 (0x0004a503) lw      a0, 0(s1)

core   0: 0x0000000000000ae4 (0x0044a583) lw      a1, 4(s1)

core   0: 0x0000000000000ae8 (0x0330000f) fence

core   0: 0x0000000000000aec (0x00c12083) lw      ra, 12(sp)

core   0: 0x0000000000000af0 (0x00042023) sw      zero, 0(s0)

core   0: 0x0000000000000af4 (0x00412483) lw      s1, 4(sp)

core   0: 0x0000000000000af8 (0x00812403) lw      s0, 8(sp)

core   0: 0x0000000000000afc (0x01010113) addi    sp, sp, 16

core   0: 0x0000000000000b00 (0x00008067) ret

core   0: 0x0000000000000b30 (0x0000006f) j       pc + 0x0

core   0: 0x0000000000000b30 (0x0000006f) j       pc + 0x0

…

Tommy

[Christopher Celio]

Hmmm, it's been awhile since I've run 32bit spike, but it looks like (on my side) I need to specify the ISA string:

spike -m2048 --isa=RV32IMAFD /install/riscv/riscv32-unknown-elf/bin/pk 

tell me what ELF to load!

-Chris

[Tommy Thorn]

Thanks Chris, that was it.

I can work the riscv-tools/README to included these pointers unless improvements are already in the works.

Tommy

[Richard Herveille]

As a totally different approach to building both 64 and 32bit versions of the tools we only build the 64bit versions and use the -m32 -march =rv32 options to specify generating and testing 32bit code. 

Richard

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[Tommy Thorn]

On Monday, May 30, 2016 at 10:07:30 PM UTC-7, richard.herveille wrote:

As a totally different approach to building both 64 and 32bit versions of the tools we only build the 64bit versions and use the -m32 -march =rv32 options to specify generating and testing 32bit code. 

Actually I'd consider that the expected path, but that is IIUC the multi-lib approach which isn't

working/implemented currently (that is, if you compile using -m32 (with or without redundant

-march=RV32I), then the link stage fails).

Are you saying it works for you?

Tommy

 

-Chris

Hi Chris,

-Chris

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[Richard Herveille]

With my set of tools it works. I noticed that -m32 does not make -march=RV32I redundant(or vice versa), even though one would expect it.

Now I have not tried the latest version of the tools and I use the newlib version (so not the riscv-linux version).  But given that, yes it works. I run the riscv64 tools and they compile and link clean 32bit code. 

What does not work is enabling (or better disabling) features using the -march option. Some functions in libc (newlib) use atomic or mul/div, which are optional in my implementation. I guess this is the multi-lib issue you are referring to?! Still linking doesn't fail, but the CPU throws an illegal exception. 

Richard

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[Tommy Thorn]

On Tuesday, May 31, 2016 at 2:22:08 PM UTC-7, richard.herveille wrote:

With my set of tools it works. I noticed that -m32 does not make -march=RV32I redundant(or vice versa), even though one would expect it.

Now I have not tried the latest version of the tools and I use the newlib version (so not the riscv-linux version).  But given that, yes it works. I run the riscv64 tools and they compile and link clean 32bit code.

If build https://github.com/riscv/riscv-tools according to the instructions under "Quickstart" then you cannot link

a helloworld.c program with -m32 (with or without -march=RV32I it's the same):

$ riscv64-unknown-elf-gcc -m32 -march=RV32I hw.c

/home/tommy/rv-build/dist64/lib/gcc/riscv64-unknown-elf/5.3.0/../../../../riscv64-unknown-elf/bin/ld: /home/tommy/rv-build/dist64/lib/gcc/riscv64-unknown-elf/5.3.0/../../../../riscv64-unknown-elf/lib/crt0

.o: ABI is incompatible with that of the selected emulation

/home/tommy/rv-build/dist64/lib/gcc/riscv64-unknown-elf/5.3.0/../../../../riscv64-unknown-elf/bin/ld: failed to merge target specific data of file /home/tommy/rv-build/dist64/lib/gcc/riscv64-unknown-elf/5.3.0/../../../../riscv64-unknown-elf/lib/crt0.o

/home/tommy/rv-build/dist64/lib/gcc/riscv64-unknown-elf/5.3.0/../../../../riscv64-unknown-elf/bin/ld: /home/tommy/rv-build/dist64/lib/gcc/riscv64-unknown-elf/5.3.0/crtbegin.o: ABI is incompatible with that of the selected emulation

...

Tommy

[Richard Herveille]

Right I remember receiving the same error, but I solved it. 

I am traveling right now. Let me take a look when I get back home. 

Richard 

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