Implementation of atomic instructions using LR/SC pair

[Sreenadh S]

In our rv64imafd multi-core  implementation, we had implemented Atomic instructions as a combination of lr and  sc instruction. Is
this implementation complaint to the risc-v specification? Will it make any
issues when running programs compiled for riscv?
Also is there any chance of following type of assembly code generated by the compiler:

lr.d x11, 0(X5)
amoadd.d X2, 0(X6)
sc.d X7, 0(x5)
[In our implementation the above sc.d will always fail]

[Charles Papon]

Hi,

From https://github.com/riscv/riscv-isa-manual/blob/23a1255de3af5d5d6a7c6993dc9f44687446c6d4/src/a.tex#L295
Seems that using atomic instruction inside a LR/SC is the issue ^^

Regards
Charles

[Bruce Hoult]

9.3 Eventual Success of Store-Conditional Instructions

• An LR/SC sequence begins with an LR instruction and ends with an SC instruction. The dynamic code executed between the LR and SC instructions can only contain instructions from the base “I” instruction set, excluding loads, stores, backward jumps, taken backward branches, JALR, FENCE, and SYSTEM instructions.  

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