Restriction of instructions during compilation

test user

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Oct 14, 2024, 11:54:03 AM10/14/24

to RISC-V SW Dev

Hi everyone,

We're trying to build a custom risc-v based processor that's going to support only a subset of the original ISA.

As a part of this, we want the compiler to restrict the instructions to a particular count instead of letting it take the Full ISA into account.

For example, we want to remove MUL instruction and keep only ADD as multiplication is repeated addition. I want to remove MUL and have branch instructions and ADD, SUB instructions only. Is there a way to directly do it through arguments or do I have to change anything in the binutils and recompile the gcc? Can someone help me here please.

Thanks,

G Kowshik

Andrew Waterman

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Oct 14, 2024, 4:23:24 PM10/14/24

to test user, RISC-V SW Dev

The RISC-V GCC port doesn't have a general mechanism to disable emission of specific instructions. The granularity is at the level of complete ISA extensions. If you need compiler support, your best bet is to implement the entire RV32I base ISA (~40 instructions).

Thanks,
G Kowshik

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Andreas Schwab

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Oct 15, 2024, 3:55:29 AM10/15/24

to Andrew Waterman, test user, RISC-V SW Dev

On Okt 14 2024, Andrew Waterman wrote:

> On Mon, Oct 14, 2024 at 8:54 AM test user <testu...@gmail.com> wrote:
>
>> For example, we want to remove MUL instruction and keep only ADD as
>> multiplication is repeated addition. I want to remove MUL and have branch
>> instructions and ADD, SUB instructions only. Is there a way to directly do
>> it through arguments or do I have to change anything in the binutils and
>> recompile the gcc? Can someone help me here please.
>>
>
> The RISC-V GCC port doesn't have a general mechanism to disable emission of
> specific instructions.

For MUL, which is its own extension (Zmmul), this is possible though.

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Andreas Schwab, SUSE Labs, sch...@suse.de
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Andrew Waterman

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Oct 15, 2024, 4:09:00 AM10/15/24

to Andreas Schwab, test user, RISC-V SW Dev

On Tue, Oct 15, 2024 at 12:55 AM Andreas Schwab <sch...@suse.de> wrote:

On Okt 14 2024, Andrew Waterman wrote:

> On Mon, Oct 14, 2024 at 8:54 AM test user <testu...@gmail.com> wrote:
>
>> For example, we want to remove MUL instruction and keep only ADD as
>> multiplication is repeated addition. I want to remove MUL and have branch
>> instructions and ADD, SUB instructions only. Is there a way to directly do
>> it through arguments or do I have to change anything in the binutils and
>> recompile the gcc? Can someone help me here please.
>>
>
> The RISC-V GCC port doesn't have a general mechanism to disable emission of
> specific instructions.

For MUL, which is its own extension (Zmmul), this is possible though.

Indeed. But the OP evidently wants to omit much more than MUL (e.g. supporting only add/sub/branch means no loads and stores), and I was trying to answer the subtextual question.

Tommy Murphy

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Oct 15, 2024, 7:35:27 AM10/15/24

to Andrew Waterman, Andreas Schwab, test user, RISC-V SW Dev

Also, disabling `M` disables more than just the `mul` instruction.

- https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1581#issuecomment-2411647734

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