aq and rl bits

[Mark Manning]

I am currently creating a forth based risc-v assember and i have a question about opcodes that have the aq and rl bits in them.  do each of these support mnemonics in all of the following formats?

xx 

xx.aq

xx.rl

xx.aqrl 

[Paul Clarke]

In the abstract, I think the answer is "yes", but some of the mnemonic-aq-rl combinations are RESERVED, so not in practice. In Zalasr, for example, the Load-Acquire instructions do not support an "rl-only" mnemonic:

> The versions without the aq bit set are RESERVED.

Similarly for the Store-Release instructions and the "rl" bit.

PC

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From: sw-...@groups.riscv.org <sw-...@groups.riscv.org> on behalf of Mark Manning <mar...@gmail.com>
Sent: Thursday, May 28, 2026 3:47 AM
To: RISC-V SW Dev <sw-...@groups.riscv.org>
Subject: [sw-dev] aq and rl bits

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[Mark Manning]

I had AI generate my tables for me because a lot of the encodings were a little difficult to figure out.  It seems to have hard coded the AQ and AL bits for fli.h fli.s fli.d and fi.q, as well as fminm and fmaxm for .s. .h, .d and .q and a whole bunch of other ZFA opcodes just to name a few.  Where it has specified hard coded values should I take its word for it?  

“When something can be read without effort,
great effort has gone into its writing.”

― Enrique Jardiel Poncela ―

[Christoph Müllner]

For the A extension LR/SC and AMO instructions, yes: the suffix corresponds
directly to the encoded aq and rl bits, so the unsuffixed, .aq, .rl, and
.aqrl forms represent the four possible bit combinations.

The caveat is that this should be per instruction definition, not a global rule
or every encoding field named aq/rl. For example, Zalasr load-acquire
instructions define the .aq and .aqrl forms, while Zalasr store-release
instructions define the .rl and .aqrl forms; the other aq/rl combinations are
reserved there.

BR
Christoph

[Paul Clarke]

I don't see that "fli.{h,s,d,q}" nor "{fminm,fmaxm}*" have AQ or RL bits. ? They don't access memory. Where do you see that those fields exist in the encoding?

> Where it has specified hard coded values should I take its word for it?

Sounds like "no", but not in the way you asked. 🙂

PC

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From: sw-...@groups.riscv.org <sw-...@groups.riscv.org> on behalf of Mark Manning <mar...@gmail.com>

Sent: Thursday, May 28, 2026 8:53 PM
Cc: RISC-V SW Dev <sw-...@groups.riscv.org>
Subject: Re: [sw-dev] aq and rl bits

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[Paul Clarke]

BTW, I'd be committing malpractice if I didn't at least point to the RISC-V Unified Database project: https://github.com/riscv/riscv-unified-db. That is exactly intended to be used for your use-case (among many others). The idea is to make the content embedded in the spec for human consumption into a database consumable by programs.

(Questions and feedback welcome. I'm a maintainer of that project.)

PC

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From: 'Paul Clarke' via RISC-V SW Dev <sw-...@groups.riscv.org>
Sent: Friday, May 29, 2026 11:32 AM
To: Mark Manning <mar...@gmail.com>

To view this discussion visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/DM6PR02MB55939BE3B621DF23537E4976E6162%40DM6PR02MB5593.namprd02.prod.outlook.com.

[ron minnich]

That URL gets a 404.

Looking forward to seeing it :-)

> To view this discussion visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/DM6PR02MB55931635709B4AC7C4FDDDCEE6162%40DM6PR02MB5593.namprd02.prod.outlook.com.

[Tommy Murphy]

> That URL gets a 404.
>
> Looking forward to seeing it :-)

Remove the extraneous trailing dot/period to get the correct URL:

https://github.com/riscv/riscv-unified-db