On 4 April 2017 at 05:58, Stefan O'Rear <
sor...@gmail.com> wrote:
> On Mon, Apr 3, 2017 at 1:05 PM, Alex Bradbury <
a...@asbradbury.org> wrote:
>> On 3 April 2017 at 19:30, Palmer Dabbelt <
pal...@sifive.com> wrote:
>>> As Alex suggested a little while ago, we're going to start bringing up
>>> toolchain interface changes on the mailing list for discussion before they go
>>> upstream, so we can avoid any interface incompatibilities.
>
> (If it wasn't already clear from the ticket, I am generally +1 on this)
>
>> Do we want to document and support -mnostrict-align while we're at it
>> as well? e.g. if I specify -mcpu=fe310 but I actually want to compile
>> my code assuming a misaligned access handler is present. For the
>> record, the ARM spellings of this functionality are
>> <
https://developer.arm.com/docs/dui0774/latest/compiler-command-line-options/-munaligned-access-mno-unaligned-access>
>> -munaligned-access and -mno-unaligned-access.
>
> My take here, which might be completely off base, is that since the
> RISC-V spec requires unaligned access (and RDCYCLE/RDTIME/RDINSTRET),
> the fact that freedom-e-sdk doesn't install handlers for unaligned
> access and timer CSRs is a bug in freedom-e-sdk and should be fixed
> there instead of in gcc.
>
> The FE310 considered in isolation is not a conforming system; if you
> choose to use the FE310 without the HiFive1 BSP you have a choice
> between implementing a trap handler to make it a conforming system
> (and this should be conspicuously noted in product documentation), or
> telling gcc to target a nonconforming system with -mstrict-align.
There seems to be a desire to support systems that implement only a
subset of functionality in the existing 'base' spec and don't provide
trap handlers. Unfortunately this further fractures the RISC-V
ecosystem - I've struggled to get an answer for the motivation behind
this <
https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/I3og57V1aHg/UbYKApQKBwAJ>.
To quote the key paragraph:
"""
As I think my emails make clear, I personally am concerned about the
downside to further subsetting the base RISC-V ISA. What I'm
struggling to understand is the upside that you see? Providing default
trap routines for misaligned access and transparently handling
rdcycle/rdtime/rdinstret is surely at worst just going to mean RISC-V
code size grows a couple of hundred bytes in a naive comparison vs
ARM. Those bytes can always be clawed back with a simple compiler flag
if someone feels happy moving away from the common base.
"""
Best,
Alex