DTS node- for RISCV AIA, IMSIC when hypervisor guest interrupt delivery is enabled

[vithurson subasharan]

Hi All, 

This doc (https://lkml.org/lkml/2023/1/3/514) indicates how dts should look like for riscv,imsics (incoming messaged signalled interrupt controller in advanced interrupt architecture). I am wondering if the CPU supports hypervisor mode and interrupt delivery to guests are enabled in the IMSIC. how would the dts's interrupt-extended field would look like. HGEIP doesn't directly have any interrupt-id assigned to it...

thanks,

Vithurson