Spike Debugging - Display register content after each cycle

[Nado]

Hi,

I am writing my own RISC-V Core and I use spike for some type of verification. Spike is very usefull but I am missing the option to automatically display the content of the registers after each cycle.

I want Spike to simulate a test program and write the whole log into a logfile but not just with the executed instruction but also the register content after each executed instruction.

Is this possible?

The command I am using right now is:

spike -l --log=spike.log --isa=rv32i main

[Charles Papon]

Hi,

So far i didn't used spike in command line, but instead integrated into the testbench itself, so i'm not sure if there is better than --log.

Be aware, to verify a core, there is things as https://github.com/SpinalHDL/rvls 
Basicaly, you colect the execution traces of your CPU, and ask rvls (which use spike internaly) to verify they are OK.
Good thing about this aproache is that tricky things as interrupt timings, peripheral readed values and multi core memory coherency can be taken in acount, allowing to go as far as verifying the traces from the a multi core system booting linux.

[Nado]

Thanks for the reply!

It looks interesting but I have problems to understand how to use it. For me its not obvious what format my trace has to be nor does the README explains it. There is an example but its not really helpful. Someone has more insight?

[Charles Papon]

The format is "specified" in https://github.com/SpinalHDL/rvls#risc-v-commands

But overal, here is how the traces are emited for NaxRiscv cpu (in a scala based hardware simulation): 

https://github.com/SpinalHDL/NaxRiscv/blob/7776f6c75394b940815e3ee229a492d51f5ecbd2/src/main/scala/naxriscv/platform/Tracer.scala#L84

For instance, when the simulation detect that the CPU commit, it add the following string to the log file : 
https://github.com/SpinalHDL/NaxRiscv/blob/7776f6c75394b940815e3ee229a492d51f5ecbd2/src/main/scala/naxriscv/platform/Tracer.scala#L94

When the cpu execute a memory load : 
https://github.com/SpinalHDL/NaxRiscv/blob/7776f6c75394b940815e3ee229a492d51f5ecbd2/src/main/scala/naxriscv/platform/Tracer.scala#L141

and so on ^^

The particularity for now is that the data / address, value are sign extended to 64 bits in the log file, that would be something to change.

[Nado]

Ah wow ok I see, thanks a lot! I will have a look!

[Phil Mulholland]

Hi,

I've written a VCD tracer for spike so I could do this.  It's on an old fork of spike, but if I find time I could update it to the latest.

https://www.five-embeddev.com/toolchain/2022/09/02/spike-fork/

It's not a text log, but VCD is a well-known format so you can convert it to text. 

Cheers,

Phil

[Nado]

Hi!

Wow this is awesome! You think it might be possible to add your changes to the main branch? I think thats a great feature. I am writing a few tutorials and it would be awesome if students could use this feature without the hassle of looking for the right branch, maintaining etc.