Zephyr RTOS support for riscv32

[Jean-Paul Etienne]

Hello RISC-V,

I have done a port of the Zephyr RTOS for the riscv32 architecture.

It currently handles the following SOCs:

• riscv32-qemu, supporting the SiFive machine model
• pulpino

You can get access to the sources at https://github.com/fractalclone/zephyr-riscv.git

The code is also currently being reviewed by the Zephyr Project at https://gerrit.zephyrproject.org

I also plan to port it to SiFive Freedom E310.

Regards,
Jean-Paul

[Stefan O'Rear]

Interesting. Does Zephyr leverage memory protection or the interrupt
controller? The privilege spec is as you are probably aware still in
a bit of flux, and we would appreciate knowing your pain points (and
other feedback items if necessary).

-s

[Stefan O'Rear]

On Fri, Dec 9, 2016 at 7:45 PM, Jean-Paul Etienne
<fracta...@gmail.com> wrote:

> Hello RISC-V,
>
> I have done a port of the Zephyr RTOS for the riscv32 architecture.

Could you add this to
https://github.com/riscv/riscv-wiki/wiki/RISC-V-Software-Status (or
provide me with text to use)?

-s

[Jean-Paul Etienne]

To be compatible with SOC like pulpino, only machine privilege level is accounted for the time being.

Regarding ISR handling:
Given that each SOC handles ISR in its own way, the port accounts for interrupt handling at two levels:
1) generic riscv32 archtiecture level, which performs interrupt handling that is common to all SOCs
2) SOC-specific level.

The architecture level expects some ISR apis to be provided by the SOC level.
This shall allow to add new SOCs without having to touch the general riscv32 architecture.
But we'll see when new SOCs will be added :-)

Regards,
Jean-Paul

[Michael]

HI Jean-Paul,

This is excellent news, thank you for the contribution. The E310 port would be very interesting too.

Best regards,

Michael

[Jean-Paul Etienne]

Hello RISC-V,

I'm very pleased to announce that the riscv32 port has successfully been merged into the Zephyr Project master repository at https://gerrit.zephyrproject.org and shall be released in Zephyr 1.7.

The riscv toolchain (gcc, binutils, gdb) and riscv-qemu have successfully been merged into the zephyr SDK and shall be released in the 0.9 SDK version.

For more information, about compiling and using it check https://github.com/fractalclone/zephyr-riscv.git
Link the zephyr-sdk-0.9 pre-release binary as well as explanation about how to use it to compile qemu_riscv32 and zedboard_pulpino boards are given.

E310 porting is under way and shall be integrated soon.

Enjoy,
Jean-Paul

[Michael Gielda]

Hi Jean-Paul, great news!

We saw that and even planned to port Zephyr to E310 this week (as you did 99% of the ground work) but since you are already working on that I think we will just wait. Unless you need help with something ;)

Best regards,

Michael

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