Bare metal booting process steps
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Susmita Nayak
May 7, 2024, 7:55:06 AMMay 7
to RISC-V SW Dev
Hi Team,
I would like to know how to visualize any bare-metal booting process on RISC-V.
Regards,
Susmita
Susmita Nayak
May 8, 2024, 2:55:31 AMMay 8
to RISC-V SW Dev
Hi Team,
It will be great if I can get any answer for this.
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Susmita Nayak
May 8, 2024, 4:49:55 AMMay 8
to Tommy Murphy, RISC-V SW Dev
Hi Tommy,
I am trying to explain the bare-metal booting process something like this as an attachment:
I was wondering if I need to represent the further steps by including the "Bootloader and kernel loading" as it's in S mode.
Please let me know if this makes sense.
On Wed, May 8, 2024 at 2:01 PM Tommy Murphy <tommy_...@hotmail.com> wrote:
I think you'll need to clarify what exactly you mean by this in order to get any feedback.
> visualize any bare-metal booting process on RISC-V.
It's too vague in my opinion. What exactly are you trying to do?
Susmita Nayak
May 9, 2024, 12:15:03 AMMay 9
to Tommy Murphy, RISC-V SW Dev
Thanks, Tommy.
I got it.
On Wed, May 8, 2024 at 9:56 PM Tommy Murphy <tommy_...@hotmail.com> wrote:
The overall context is still unclear to me.You mention bare-metal but then also mention OpenSBI and kernel which suggests that it's not actually bare-metal but maybe an RTOS or even a "full featured" OS like Linux?How RISC-V boots an OS/Linux using stuff like UEFI, Das U-Boot, OpenSBI etc. is explained in detail elsewhere already.For example there are several YouTube videos on this topic:
Dan Petrisko
May 9, 2024, 1:11:32 AMMay 9
to Susmita Nayak, Tommy Murphy, RISC-V SW Dev
Perhaps of use?
Best,
-Dan
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ron minnich
May 12, 2024, 11:15:37 AMMay 12
to Dan Petrisko, Susmita Nayak, Tommy Murphy, RISC-V SW Dev
Those are good summary slides, I want to point out a few things:
The 2015 coreboot work included an SBI. We've recently revived that SBI for coreboot, as it is considerably simpler, and relies on the new Linux support for
handling load/store traps. I recently removed the unaligned load/store support; in 2015, it was very small, but by 2024, with the growing complexity of RISC-V, the code had ballooned, and I don't trust C code that large, ever. Plus, somebody had "improved" it at some point, trying to catch up with the ever-more-complex risc-v architecture, and it was not working in all cases any more anyway.
The comment that coreboot does not support SMP is not quite right IMHO. The SMP startup in RISC-V was always assumed to happen in kernel, with spinloops,
coreboot for risc-v was upstreamed in 2014 for rv-32, and 2015 for rv64, in priv mode, i.e., not 2019 as mentioned in the slides. oreboot (Rust) was released in 2019. As Rust capabilities have grown, oreboot went through an almost complete rewrite in 2022, becoming smaller and better. I removed 80KLOC that we no longer needed.
The 2015 coreboot work included an SBI. We've recently revived that SBI for coreboot, as it is considerably simpler, and relies on the new Linux support for
handling load/store traps. I recently removed the unaligned load/store support; in 2015, it was very small, but by 2024, with the growing complexity of RISC-V, the code had ballooned, and I don't trust C code that large, ever. Plus, somebody had "improved" it at some point, trying to catch up with the ever-more-complex risc-v architecture, and it was not working in all cases any more anyway.
The comment that coreboot does not support SMP is not quite right IMHO. The SMP startup in RISC-V was always assumed to happen in kernel, with spinloops,
although that is now deprecated in favor of HSM (which adds still more complexity and state in SBI, which worries me). I still would prefer to have Linux handle SMP startup, but that's not going to happen.
If you want to try a simpler SBI, you can look at coreboot's implementation, though it is not caught up with the SBI spec, which literally changes monthly. If you want to get away from C (good idea!) you can check out RustSBI, which is used in oreboot. OpenSBI is the most up to date and compliant with the spec.
I'm experimenting with an SBI in Go, using TinyGo, because TinyGo compiled code is competitive with, and sometimes better than, Rust on size, speed, and jitter measures. That surprised me too, but the TinyGo project is really something.
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