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regards,
Liviu
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In SysML, I think it looks like this … I hope everyone can see:
From: Rishiyur Nikhil [mailto:nik...@bluespec.com]
Sent: Friday, November 17, 2017 5:24 PM
To: Liviu Ionescu <i...@livius.net>
Cc: atish patra <atis...@gmail.com>; RISC-V SW Dev <sw-...@groups.riscv.org>; tommy_...@hotmail.com; pal...@sifive.com
Subject: Re: [sw-dev] Definition of "hart"
EXTERNAL EMAIL
> ... it's all about the registers.
But this is true even of software threads.
Shouldn't the definition be sharper, to avoid such "virtualization" of registers?
I.e., that the registers can be "simultaneously/concurrently" active?
Nikhil
On Fri, Nov 17, 2017 at 8:05 PM, Liviu Ionescu <i...@livius.net> wrote:
> On 18 Nov 2017, at 02:58, atish patra <atis...@gmail.com> wrote:
>
> As I understood, the core concept is similar to hyper-threads in x86.
I would say that the hart concept is similar to hyper-threads in x86; core is more or less the same in both architectures.
regards,
Liviu
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- some say a key point is that a hart lacks independent instruction fetch, others say that's not relevant (or not necessarily the case?)
- independent registers doesn't seem to distinguish it from a software thread with "virtual" independent registers
- having to extrapolate from x86 documentation to what hart means to RISC-V specifically isn't clear
The fact that nobody can give a clear and concise definition of the term/concept hart suggests to me that it's not widely or consistently understood. Dutch a definition does not appear in the specs or any third party RISC-V online or printed material that I have read so far either.
The specs really should provide such a definition in my opinion since it seems so fundamental to understanding RISC-V.
Thanks
Is there a clear, concise and authoritative definition of the term/concept "hart" anywhere?The spec doesn't seem to have one and simply uses the term without any specific explanation so it remains unclear/ambiguous.Thanks.