Help, entering supervisor mode get instruction page fault

[Daniel Lu]

Hi all

The topic is self explained, when I trying to enter supervisor mode, somehow, I get Instruction page fault exception (0xc). the exact instruction cause excpt is mret. what could be the problem?

I dumpped some of csr register just before mret:
pmpaddr0: 0x000000003FFFFFFF
pmpcfg0: 0x000000000000001F
mstatus: 0x0000000000000800
mepc: 0x000000009F0000D0
mtvec: 0x0000000000010048

my code for enter supervisor mode is following.

    long pmpcfg0 = 0x1f;
    char* ptr=&_start;
    long v;
    asm volatile ("li t6, -1\n\t"
                      "csrw pmpaddr0, t6\n\t"
                      "csrw pmpcfg0, %1\n\t"
                      "li t5, 0x800\n\t"
                      "csrs mstatus, t5\n\t"
                      "li t5, 0x88\n\t"
                      "csrc mstatus, t5\n\t"
                      "csrw mepc, %0"::"r"(ptr),"r"(pmpcfg0):"t5","t6");
    DUMP_CSR_REGISTER(pmpaddr0,v);
    DUMP_CSR_REGISTER(pmpcfg0,v);
    DUMP_CSR_REGISTER(mstatus,v);
    DUMP_CSR_REGISTER(mepc,v);
    DUMP_CSR_REGISTER(mtvec,v);
    asm volatile ("mret");

don't be confused by _start, it is just the start physical address of supervisor mode code. I trace the wave of cpu, after mret, the PC correctly set to target address, but instruction is not fetched, and 0xc is raised.
the pmpaddr0 part confusing me for a while, I give myself a explain becaue I have only 512M share memory.  isn't it?

[Hesham Almatary]

Hi Daniel,

Have you created page tables and set up proper mappings (including
writing satp register)? If not, this might be the problem.

Cheers,
Hesham

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[Daniel Lu]

Hi Hesham,

No, I haven't.  supervisor code is Linux, I think it will setup page table. Linux code will setup page table very short(several instructions later) after go into supervisor mode, I do see some code like(setup_vm to do it). If I setup page table, it would only serve the several instructions? My real question here is: 

   1. Do I have to setup page table to translate the physical address to virtual address, even if I don't need it while I'm using mret to enter supervisor?

   2. I know linux va start address is 0xfffff..f80000000, aka. page offset. but vmlinux image(binary format) is relative to 0 offset, all linux internal address should be relative address. so, do I have to setup page table in order to  translate my vmlinux load PA to this VA? or I could just setup a page table hierarchy to do a pa==va fake mapping, and let linux to do the job for setup up a real page table?

sorry for these linux related question, I'm not very familiar with linux startup code, these questions do looks like linux related but they also tight connect to RISC-V supervisor mode.

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Hesham

[Richard W.M. Jones]

On Thu, Mar 29, 2018 at 11:12:44AM +0800, Daniel Lu wrote:
> Hi Hesham,
>
> No, I haven't. supervisor code is Linux, I think it will setup page table.
> Linux code will setup page table very short(several instructions later)
> after go into supervisor mode, I do see some code like(setup_vm to do it).
> If I setup page table, it would only serve the several instructions? My
> real question here is:
> 1. Do I have to setup page table to translate the physical address to
> virtual address, even if I don't need it while I'm using mret to enter
> supervisor?
> 2. I know linux va start address is 0xfffff..f80000000, aka. page
> offset. but vmlinux image(binary format) is relative to 0 offset, all linux
> internal address should be relative address. so, do I have to setup page
> table in order to translate my vmlinux load PA to this VA? or I could just
> setup a page table hierarchy to do a pa==va fake mapping, and let linux to
> do the job for setup up a real page table?
>
> sorry for these linux related question, I'm not very familiar with linux
> startup code, these questions do looks like linux related but they also
> tight connect to RISC-V supervisor mode.

Did you look into how riscv-pk does it? This is the code that enters
the kernel, where fn is the kernel entry point, arg0 is the hart
number, arg1 is the address of the DTB located on the next page
boundary after the kernel:

https://github.com/riscv/riscv-pk/blob/dcd6ee0893f784320db857cb66f8424a1d154d8d/machine/minit.c#L175

Rich.

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[Daniel Lu]

I did reference riscv-pk code for entering s mode. a0 is mhartid, a1 is dtb pointer, as I mentioned,actually, the exception raise on mret, linux kernel no chance to read reg yet.

Richard W.M. Jones <rjo...@redhat.com> 于 2018年3月30日周五 18:06写道：