riscv-opcodes wasn't added to FSF binutils, so it not being used to
maintain the assembler/disassembler, though I don't know if it was
ever used for that. The info in this URL looks OK. And the fact it
works for mod seems to indicate that it is OK. if it isn't working
for your mac instruction then maybe you made a mistake.
Actually, looking at this again, I see you want an instruction with 3
inputs, but are using an instruction format that only supports 2 input
registers. Maybe compiler optimization is changing the destination
register, which is breaking your attempt to use the destination
register as an input. You also need to modify the asm to indicate
that the destination is also an input. You can do this by changing
: [z] "=r" (c)
to
: [z] "+r" (c)
However, it would be best if you used an instruction format that
properly supports 3 input registers to avoid confusion. See for
instance the fmadd instructions, though since you want to do this for
an integer instruction, you will need more changes to add operand
description letters for a third input, which will require
gas/config/tc-riscv.c changes.
it is probably easier is you just use .insn instead.
Jim