Custom instructions

164 views
Skip to first unread message

arup de

unread,
Jul 3, 2018, 1:30:27 PM7/3/18
to sw-...@groups.riscv.org
Hi,
How to add a custom instruction? I would like to add ‘mac ‘ instruction ( a=a+b*c) where it used rd’s current value to compute the final. I tried the steps available at web. However, the assembler is not generating the correct operands. I expected
mac a3, a4, a5
But it actually generated
mac a5, a4, a5
Please let me know how to fix it.


Thanks,
Arup




Sent from my iPhone

Jim Wilson

unread,
Jul 3, 2018, 1:52:41 PM7/3/18
to arup de, RISC-V SW Dev
On Tue, Jul 3, 2018 at 10:30 AM, arup de <aru...@gmail.com> wrote:
> How to add a custom instruction? I would like to add ‘mac ‘ instruction ( a=a+b*c) where it used rd’s current value to compute the final. I tried the steps available at web. However, the assembler is not generating the correct operands. I expected
> mac a3, a4, a5
> But it actually generated
> mac a5, a4, a5

What instructions on which web site? You haven't given us any useful
info to respond to.

FSF binutils development tree has support for .insn which allows you
to construct custom instructions. There is documentation for this in
the gas manual in the development tree. See for instance
https://sourceware.org/ml/binutils/2018-03/msg00152.html

Jim

arup de

unread,
Jul 3, 2018, 2:48:03 PM7/3/18
to Jim Wilson, RISC-V SW Dev
I followed below link description to add custom instructions. It works fine for mod instruction as described in the link. However, it didn’t work for mac instruction. Please see the link below.

Jim Wilson

unread,
Jul 3, 2018, 3:09:03 PM7/3/18
to arup de, RISC-V SW Dev
On Tue, Jul 3, 2018 at 11:47 AM, arup de <aru...@gmail.com> wrote:
> I followed below link description to add custom instructions. It works fine
> for mod instruction as described in the link. However, it didn’t work for
> mac instruction. Please see the link below.
>
> https://nitish2112.github.io/post/adding-instruction-riscv/

riscv-opcodes wasn't added to FSF binutils, so it not being used to
maintain the assembler/disassembler, though I don't know if it was
ever used for that. The info in this URL looks OK. And the fact it
works for mod seems to indicate that it is OK. if it isn't working
for your mac instruction then maybe you made a mistake.

Actually, looking at this again, I see you want an instruction with 3
inputs, but are using an instruction format that only supports 2 input
registers. Maybe compiler optimization is changing the destination
register, which is breaking your attempt to use the destination
register as an input. You also need to modify the asm to indicate
that the destination is also an input. You can do this by changing
: [z] "=r" (c)
to
: [z] "+r" (c)

However, it would be best if you used an instruction format that
properly supports 3 input registers to avoid confusion. See for
instance the fmadd instructions, though since you want to do this for
an integer instruction, you will need more changes to add operand
description letters for a third input, which will require
gas/config/tc-riscv.c changes.

it is probably easier is you just use .insn instead.

Jim

Sathya Narayanan N

unread,
Jul 4, 2018, 2:18:11 AM7/4/18
to ji...@sifive.com, aru...@gmail.com, sw-...@groups.riscv.org
Hi,

you need to make changes to the assembler part. At Shakti (IIT Madras), we have added support for the extended bit manipulation instructions to the riscv assembler.

Roughly the procedure to be followed for adding instructions are:

Addition of instructions:

● Go to riscv-tools/riscv-opcodes/opcodes. All the instructions will be written there in a
specific format. The format will also be mentioned in the file. Instructions will also be
grouped together in a specific logic. Choose which logic is more suitable for the custom
instruction and then add it to that group. For example, the instruction added is ‘ctz’, it can
be

● Then, run the following command from the riscv-opcodes folder terminal to obtain the
match and mask code.

      ○ cat opcodes-pseudo opcodes opcodes-rvc opcodes-rvc-pseudo opcodes-custom | ./parse-opcodes -c > <path name>/temp.h

● Go to the temp.h and copy the match and mask code. 

● Paste the match and mask code in the
riscv-gnu-toolchain/riscv-binutils-gdb/include/riscv-opc.h

● Then , the instruction is initialised by going to
  riscv-gnu-toolchain/riscv-binutils-gdb/opcode/riscv-opc.c

○ The constructors have various parameters such as type of instruction (I for
immediate and C for compressed) and operands, where in most cases, the
variables given will be d(destination), s(source), t(transition).

regards,
sathya



--
You received this message because you are subscribed to the Google Groups "RISC-V SW Dev" group.
To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+un...@groups.riscv.org.
To post to this group, send email to sw-...@groups.riscv.org.
Visit this group at https://groups.google.com/a/groups.riscv.org/group/sw-dev/.
To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/CAFyWVaZTZapvJvtH9ZDw8fijD9zR6b33eRqe7Oj%3Dc4twndqzPA%40mail.gmail.com.


--
 regards,
Sathya  

 

arup de

unread,
Jul 4, 2018, 4:19:51 AM7/4/18
to Sathya Narayanan N, Jim Wilson, RISC-V SW Dev
Hi Sathya and Jim,
       Thanks. Is it possible to create a custom instruction with 4 operands?

Thanks,
Arup


To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+unsubscribe@groups.riscv.org.


--
 regards,
Sathya  

 

Luke Kenneth Casson Leighton

unread,
Jul 4, 2018, 6:28:09 AM7/4/18
to arup de, Sathya Narayanan N, Jim Wilson, RISC-V SW Dev
On Wed, Jul 4, 2018 at 9:19 AM, arup de <aru...@gmail.com> wrote:

> Hi Sathya and Jim,
> Thanks. Is it possible to create a custom instruction with 4
> operands?

p.136 (table 22.2) v2.3-draft risc-v isa manual shows you some of the
types of *standard* instructions (and p134 shows more). one of them
is called "R4 type". so the answer's yes.

31 27 26 25 24 20 19 15 14 12 11 7 6 0
funct7 rs2 rs1 funct3 rd opcode R-type
rs3 funct2 rs2 rs1 funct3 rd opcode R4-type
imm[11:0] rs1 funct3 rd opcode I-type
imm[11:5] rs2 rs1 funct3 imm[4:0] opcode S-type

rdest, rsource1-3... that's 4. so, look in binutils source code for
clues based around an "R4 type" ok?

but remember, also, custom instructions, you can do anything you like.
the question is, how much time and money do you have to deviate from
the path that everyone else is taking (and how much long-term
maintenance time are you willing to put in)?

l.
Reply all
Reply to author
Forward
0 new messages