generating .hex for latest riscv-tools

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Richard Herveille

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Jan 30, 2017, 10:29:44 AM1/30/17
to sw-...@groups.riscv.org, Richard Herveille
I thought I’d update my regression suite again, based on/using the latest tests on github.
It seems a lot changed in the overal setup since my last update.
Worst change, for me, is that I can’t generate .hex files anymore; I get some error on ../fesvr/htif_hexwrtie.cc:15 virtual void htif_hexwriter_t::read_chunk(adds_t, size_t, void*): Assertion ‘taddr < width*depth’ failed.

Does anybody have an idea what that means?!
I used to run the .hex files in my hardware simulation (not in spike). My test bench picks up the .hex files, writes it into memory and launches the CPU.

Richard



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Colin Schmidt

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Jan 30, 2017, 11:43:43 AM1/30/17
to Richard Herveille, sw-...@groups.riscv.org
After the memory map changed programs begin at 0x80000000 and so elf2hex thinks this address is out of the requested range( 0 to width*depth). Depending on how you have been loading the hex files you may be able to specify this offset or work around it in some other way, in which case you can just change the assertion to take into account you are only generating a hex for addresses past 0x80000000. Rocket-chip no longer supports loading programs via hex file so the generation of .hex has lower priority.

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Neel Gala

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Jan 30, 2017, 12:50:38 PM1/30/17
to RISC-V SW Dev, richard....@roalogic.com, col...@eecs.berkeley.edu
I too use .hex files for running my hw simulations. As of now I am using the following "hack" to generate a valid hex which starts from 0x80000000.
Obviously my testbench treats 0x8******* as 0x0******* for now.

riscv64-unknown-elf-objcopy -O verilog -j .text -j .tohost -j .data --gap-fill 00000000 --reverse-bytes=4 output.riscv temphex
sed -i 's/ //g' temphex"
gen_usable_hex.py # this code is presented below.

#!/usr/bin/env python

import config
import textwrap

infile=open('temphex','r')
outfile=open('code.hex','w')
for lineno,line in enumerate(infile):
  if('@' in line):
    continue
  else:
    line=textwrap.wrap(line,8)
    for i in range(len(line)):
      outfile.write(line[i])
      outfile.write("\n") 
    if(config.sperateInstrDataMemory==True):
      if('0000006f' in line):
        outfile.close();
        outfile=open('memory.hex','w');

infile.close()
outfile.close()

For now this procedure works for us. You can also visit our shakti repo for more details.


On Monday, January 30, 2017 at 10:13:43 PM UTC+5:30, Colin Schmidt wrote:
After the memory map changed programs begin at 0x80000000 and so elf2hex thinks this address is out of the requested range( 0 to width*depth). Depending on how you have been loading the hex files you may be able to specify this offset or work around it in some other way, in which case you can just change the assertion to take into account you are only generating a hex for addresses past 0x80000000. Rocket-chip no longer supports loading programs via hex file so the generation of .hex has lower priority.
On Mon, Jan 30, 2017 at 7:29 AM, Richard Herveille <richard....@roalogic.com> wrote:
I thought I’d update my regression suite again, based on/using the latest tests on github.
It seems a lot changed in the overal setup since my last update.
Worst change, for me, is that I can’t generate .hex files anymore; I get some error on ../fesvr/htif_hexwrtie.cc:15 virtual void htif_hexwriter_t::read_chunk(adds_t, size_t, void*): Assertion ‘taddr < width*depth’ failed.

Does anybody have an idea what that means?!
I used to run the .hex files in my hardware simulation (not in spike). My test bench picks up the .hex files, writes it into memory and launches the CPU.

Richard



ROA LOGIC
Design Services and Silicon Proven IP

Richard Herveille
Managing Director
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Richard Herveille

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Jan 31, 2017, 7:01:09 AM1/31/17
to Neel Gala, Richard Herveille, RISC-V SW Dev, col...@eecs.berkeley.edu
Hehehe, this seems the world upside down. I usually generate verilog files from the .hex files.

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Richard Herveille

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Jan 31, 2017, 7:02:42 AM1/31/17
to Colin Schmidt, Richard Herveille, sw-...@groups.riscv.org
I might give this a go.
What argument name would you propose? I’ll take a look at the code to see if I am able to add this.

Richard


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On 30 Jan 2017, at 18:22, Colin Schmidt <col...@eecs.berkeley.edu> wrote:

It changed in this commit(https://github.com/riscv/riscv-tools/commit/40a956a7a5335c051416a69eed7d28936b8d967a). I'm not sure where it lives in the spec. You should be able to just subtract that address from taddr in the assertion and where elf2hex does the writing, to work around this issue. A better way to support it that could be upstreamed would probably be another argument to elf2hex that gives the offset to start at.

On Mon, Jan 30, 2017 at 9:12 AM, Richard Herveille <richard....@roalogic.com> wrote:
This is not Rocket (there are other hardware implementation out there too :-).
For embedded applications .hex is still the way to go. Support for generating .hex files must be part of the toolchain.

Then this is not related to loading the hex file, but to actually generating it. I don’t need fesvr, but still elf2hex seem to think it is needed. Is this hardcoded somewhere?
Second is there a description of the new memory map? I can’t find it in the privileged spec.

Richard



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On 30 Jan 2017, at 17:43, Colin Schmidt <col...@eecs.berkeley.edu> wrote:

After the memory map changed programs begin at 0x80000000 and so elf2hex thinks this address is out of the requested range( 0 to width*depth). Depending on how you have been loading the hex files you may be able to specify this offset or work around it in some other way, in which case you can just change the assertion to take into account you are only generating a hex for addresses past 0x80000000. Rocket-chip no longer supports loading programs via hex file so the generation of .hex has lower priority.
On Mon, Jan 30, 2017 at 7:29 AM, Richard Herveille <richard.herveille@roalogic.com> wrote:
I thought I’d update my regression suite again, based on/using the latest tests on github.
It seems a lot changed in the overal setup since my last update.
Worst change, for me, is that I can’t generate .hex files anymore; I get some error on ../fesvr/htif_hexwrtie.cc:15 virtual void htif_hexwriter_t::read_chunk(adds_t, size_t, void*): Assertion ‘taddr < width*depth’ failed.

Does anybody have an idea what that means?!
I used to run the .hex files in my hardware simulation (not in spike). My test bench picks up the .hex files, writes it into memory and launches the CPU.

Richard



ROA LOGIC
Design Services and Silicon Proven IP

Richard Herveille
Managing Director
Cell +31 (6) 5207 2230





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Wei Song

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Jan 31, 2017, 9:01:27 AM1/31/17
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Colin Schmidt

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Jan 31, 2017, 2:04:38 PM1/31/17
to Wei Song, Richard Herveille, sw-...@groups.riscv.org
That looks like what I was imagining. I think just getting that to apply cleanly to master would be a good PR.

On Tue, Jan 31, 2017 at 6:01 AM, Wei Song <ws...@cam.ac.uk> wrote:

On 31/01/17 12:02, Richard Herveille wrote:
I might give this a go.
What argument name would you propose? I’ll take a look at the code to see if I am able to add this.

Richard


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On 30 Jan 2017, at 18:22, Colin Schmidt <col...@eecs.berkeley.edu> wrote:

It changed in this commit(https://github.com/riscv/riscv-tools/commit/40a956a7a5335c051416a69eed7d28936b8d967a). I'm not sure where it lives in the spec. You should be able to just subtract that address from taddr in the assertion and where elf2hex does the writing, to work around this issue. A better way to support it that could be upstreamed would probably be another argument to elf2hex that gives the offset to start at.
To unsubscribe from this group and stop receiving emails from it, send an email to sw-dev+unsubscribe@groups.riscv.org.

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Richard Herveille

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Jan 31, 2017, 2:13:41 PM1/31/17
to Colin Schmidt, Wei Song, sw-...@groups.riscv.org
In that case ...

Hi Wei,

Will you create a pull request or should I apply your changes here and create a pull request?

Richard


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Wei Song

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Jan 31, 2017, 2:40:36 PM1/31/17
to Richard Herveille, Colin Schmidt, sw-...@groups.riscv.org
I will send a PR soon. Thanks.  -Wei

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Wei Song

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Feb 1, 2017, 7:27:36 AM2/1/17
to Richard Herveille, Colin Schmidt, sw-...@groups.riscv.org

A PR has been submitted to riscv-fesvr.   -Wei

Suseela Budi

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Apr 24, 2017, 7:40:12 AM4/24/17
to RISC-V SW Dev, richard....@roalogic.com, col...@eecs.berkeley.edu, ws...@cam.ac.uk
Now if I change imem Origin from 0x80000000 to others (ex: 0x00000000) in linker command file (.ld), it is giving following error while hex generation.

elf2hex: ../fesvr/htif_hexwriter.cc:40: virtual void htif_hexwriter_t::write_chunk(addr_t, size_t, const void*): Assertion `taddr < width*depth' failed.
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steven

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Apr 29, 2017, 1:10:34 AM4/29/17
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I'm new to riscv and is more of hardware engineer . What I need is writing my own c program (no libarary needed) and compile it into either hex or binary file. And reading it into an internal ram where program counter starts to fetch. I just want to run in vsim ，pure verilog approach.

Can someone guild me how to do this ？ it wold be good if you could share an example since I really don't know too much software knowledge.

Thanks
Steven


Suseela Budi於 2017年4月24日星期一 UTC+8下午7時40分12秒寫道：

Richard Herveille

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Apr 29, 2017, 2:30:51 AM4/29/17
to steven, RISC-V SW Dev, col...@eecs.berkeley.edu, ws...@cam.ac.uk
Objcopy is the tool you want.
Alternatively use Eclipse-CDT with the risc-v plugin. It gives you a software development environment with all the tools setup, including hex, bin, or verilog format generation.

Richard



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Sober Liu

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Apr 30, 2017, 9:38:56 PM4/30/17
to Richard Herveille, steven, RISC-V SW Dev, col...@eecs.berkeley.edu, ws...@cam.ac.uk
For me, I sync updated riscv-fesvr beside riscv-tool:
riscv-fesvr riscv-tools

And updated build-spike-only.sh to overwrite default build fesvr:
build_project ../riscv-fesvr --prefix=$RISCV
build_project riscv-isa-sim --prefix=$RISCV --with-fesvr=$RISCV

In this way elf2hex support additional option to give a base address.
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Tommy Murphy

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May 1, 2017, 4:15:57 AM5/1/17
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objcopy -adjust-start?

https://sourceware.org/binutils/docs/binutils/objcopy.html

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