Question about experimenting with RISC-V P extension (toolchain / simulator)

[Thang Trang]

Hi,

I'm a final-year student working on my undergraduate thesis related to the RISC-V Packed SIMD P extension.

I'm currently studying the draft specification "Preliminary in-progress RISC-V P Extension Version 0.12-draft (2026-03-08)" and trying to build a small experimental environment to understand and test some of the instructions.

I would like to ask:

1. Is there any Spike, Sail, or QEMU implementation that supports the P extension?

2. If not, what would be the recommended starting point to prototype these instructions?

3. Is modifying Spike decode tables and instruction semantics a reasonable approach for experimentation?

My goal is only to run small test programs and study the behavior of packed SIMD instructions for my thesis.

Any suggestions or references would be greatly appreciated.

Thanks.

[Rich Fuhler]

Hi Thang,

Jiawei can best answer your questions. 

-rich

-------- Original message --------

From: Thang Trang <trangt...@gmail.com>

Date: 3/9/26 3:51 AM (GMT-08:00)

To: RISC-V SW Dev <sw-...@groups.riscv.org>

Subject: [sw-dev] Question about experimenting with RISC-V P extension (toolchain / simulator)

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[Thang Trang]

Hi Rich,

Thanks for the pointer.

Hi Jiawei, if you're on this thread, I would really appreciate any insights you might have regarding experimentation with the RISC-V P extension.

Best regards,
-Thang

Vào lúc 19:14:22 UTC+7 ngày Thứ Hai, 9 tháng 3, 2026, Rich Fuhler đã viết:

[Thang Trang]

Hi Jiawei,

Thank you for your response and for sharing the QEMU implementation.

I noticed that in the QEMU repository (dev-p-018 branch) the P extension seems to follow version 0.18. However, when I checked the RISC-V P extension specification at https://github.com/riscv/riscv-p-spec, the latest version I could find is v0.12.

Could you please let me know where I can find the specification for version 0.18, or if there is a draft available somewhere?

Thank you very much for your help.

Best regards,
Thang

On Tue, Mar 10, 2026 at 9:06 AM Jiawei <jia...@iscas.ac.cn> wrote:

Hi Tang,

We have implemented the QEMU supports for P extension.

You can check it in https://github.com/mollybuild/qemu/tree/dev-p-018

Since I'm not an expert for simulator part, maybe you can ask the committer in QEMU repo.

Best,
Jiawei

[Thang Trang]

Hi Jiawei

Thank you very much for the clarification and the references.  

BR,

Thang

On Tue, Mar 10, 2026 at 3:43 PM Jiawei <jia...@iscas.ac.cn> wrote:

Hi Tang,

Sorry for not explain the version clearly, the QEMU is implemented based on John Hauser's document https://www.jhauser.us/RISCV/ext-P/

And RISC-V P extension specification at github https://github.com/riscv/riscv-p-spec is also base form John Hauser's document.

The encoding and description are the same but github version is using ascii for review.

BR,

Jiawei