Building a cycle accurate NoC simulation

[Adrian McMenamin]

I know many may think this is a task that will lead on to madness, but it is what it is...

I need/want to build a cycle-accurate (or in some other way timing-accurate) simulation of a many-core NoC using Riscv. I have now come to realise that my first idea - to hack away at Spike is likely to fail because it's fundamentally not built to be cycle-accurate.

Does this mean that the best approach is to use the rocket resources - found here https://github.com/ucb-bar ?

And before I plunge in further does anyone have any sage words of advice?

Many thanks

Adrian

[Michael Chapman]

Work out what it is you want to measure.

Then decide whether you really need something cycle accurate or not.
If it has to be cycle accurate, then put it on a big FPGA along with instrumentation to measure what you need.

I suspect that you do not need even a model of Riscv for what you want to achieve. A transaction model of the NoC and a model of the transactions you will generate will probably be the best way to go.

Don't go over the top on detail when it is not needed.

[Adrian McMenamin]

On Thursday, 14 July 2016 23:34:53 UTC+1, Michael Chapman wrote:

Work out what it is you want to measure.

I have. The timing performance. Experience has taught me that wall clock measures are not good for this as then you are dependent on the scheduling mechanisms of the operating system you are running this on. Instead you have to count something in the simulation and cycles are usually the easiest, but I am open to other suggestions.

 

Then decide whether you really need something cycle accurate or not.
If it has to be cycle accurate, then put it on a big FPGA along with instrumentation to measure what you need.

Not a serious option for simulating a 256 core NoC at this point.

 

I suspect that you do not need even a model of Riscv for what you want to achieve. A transaction model of the NoC and a model of the transactions you will generate will probably be the best way to go.

I have already built one of these. But it's not of sufficient rigour.

 

[Christopher Celio]

Hi Adrian, 

I have. The timing performance. Experience has taught me that wall clock measures are not good for this as then you are dependent on the scheduling mechanisms of the operating system you are running this on. Instead you have to count something in the simulation and cycles are usually the easiest, but I am open to other suggestions.

Not a serious option for simulating a 256 core NoC at this point.

I have already built one of these. But it's not of sufficient rigour.

You are asking how to do something that is bleeding-edge computer architecture research- a 256-core cycle-exact simulation on the scale of multiple OS quantums.  Off the top of my head, you would need a full FPGA cluster to do this.  And despite the incredible effort to build it with a realistic timing model, you'd likely still run into problems of rigour, applicability, and believability.

-Chris

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[Ma vincent]

hi Adrian,

Do you want to run linux in your 256 core processor? We are working on a open source project which has a instruction accurate SystemC model, a cycle accurate SC model, and verilog code. But it is still too simple and can only run rtos. If it is useful to you, please tell me.

best,

Vincent

---

发件人: Adrian McMenamin <adrianm...@gmail.com>
发送时间: 2016年7月15日 9:47
收件人: RISC-V SW Dev
主题: [sw-dev] Re: Building a cycle accurate NoC simulation

 

[Stefan O'Rear]

On Thu, Jul 14, 2016 at 3:01 PM, Adrian McMenamin
<adrianm...@gmail.com> wrote:
> I know many may think this is a task that will lead on to madness, but it is
> what it is...
>
> I need/want to build a cycle-accurate (or in some other way timing-accurate)
> simulation of a many-core NoC using Riscv. I have now come to realise that
> my first idea - to hack away at Spike is likely to fail because it's
> fundamentally not built to be cycle-accurate.

(forgot how replies work. Sending this to the whole list this time, sorry.)

A minor point compared to the others, but "cycle-accurate RISC-V
simulator" is a category error - RISC-V does not specify timing.
Timing is a microarchitectural and system concern, you could make a
cycle-accurate simulator for a variety of different RISC-V based
systems, including the UCB Rocket-chip SOCs but also other
possibilities.

> Does this mean that the best approach is to use the rocket resources - found
> here https://github.com/ucb-bar ?

The rocket resources will give you a netlist-level simulation, which
is much more than you need. A cycle-accurate software simulator of
the rocket-chip system would likely be a couple orders of magnitude
faster than the verilog simulation.

> And before I plunge in further does anyone have any sage words of advice?

A cacheless, non-pipelined design which always runs at 1 CPI would not
be very practical to build, but it'd be much easier to simulate than a
practical design, and might still give you what you need. There are
other possibilities, like instrumenting only branches.

What are you trying to get out of the simulation? Is it possible that
the same results would be easier to get by instrumenting "valgrind" or
"rr"?

-sorear

[filderbär]

Hi Vincent,

Could you please post a link to your mentioned open source project?

Thanks very much.

Best regards,

Filderbär

[kritik bhimani]

http://www.opensocfabric.org/home.php 

https://github.com/LBL-CoDEx/OpenSoCFabric