Debug SoC Running on Digilent Genesys connected to freedom studio platform via JTAG for debugging the RISC -V CPU

[Akhil Suresh]

Hi, 

i was about to check the debug and trigger  capabilities of my risc v processor by integrating a debug and trigger set in the CPU and connecting a external debugger during soc integration. i have generated a bit stream and programmed Genesys 2 board also written contrains to map my pmode pins to connect jtag . i have programmed rom with a boot loader.

i have set up the jtag connection with my host pc having freedom studio set up and  a compiled a code in it but on trying to send the compile code via jtag to halt,set breakpoint via jtag i am getting an error . 

Could anyone help me with finding out what the error is is it a problem with my CPU or external debugger or even a problem with SoC integration?

i have tested similar setup on my 64 bit CPU which is working fine but the issue is with 32 bit CPU. I am attaching the error herewith for reference

[Tommy Murphy]

You should probably try to get the debug connection working standalone outside of any IDE first to eliminate unnecessary complications.

E.g. you seem to be using a J-Link and the Segger software to connect rather than, say, OpenOCD, so you should try using that software alone to see if you can get a connection. Verbose logs may help identify what's going on/wrong. 

It looks like it's maybe (I'm not sure and haven't used J-Kink for a while now) getting a basic connection but then the target isn't halting properly after reset/halt. It's difficult to speculate why this might be happening without more details.

You could also maybe try OpenOCD to see if that behaves why differently. If the same issue occurs there then you should look at the verbose openocd -d3 log for clues as to what's happening.

BTW It's better to post logs rather than screenshots as the latter aren't easy for everybody to view and they don't facilitate searching/processing of text information etc.