JumpStart: Framework for writing diags (tests) for RISC-V CPU/SOC validation

[Jerin Joy]

Rivos is open sourcing JumpStart which provides Design Validation engineers a framework with which to write diags (tests) for RISC-V CPU and SOC validation:

https://github.com/rivosinc/jumpstart

JumpStart includes a bare-metal kernel, APIs and build infrastructure. It is used internally for design validation at Rivos and is in active development.

Diags can be written in C and/or RV64 Assembly and use the APIs provided by JumpStart. The diags built with JumpStart can be run on the Spike simulator by default and enhanced to run on any RV64 RISC-V system. 

A breakdown of an example diag written using JumpStart:

https://github.com/rivosinc/JumpStart/blob/main/docs/quick_start_anatomy_of_a_diag.md

For more details, please refer to the README and Reference Manual in the repo.

Jerin

[Daniel Petrisko]

Wow, thanks for sharing! This is the most comprehensive open-source PTE generation I have seen, excited to give it a shot. 

I may have missed it, but are there capabilities to trigger interrupts in diags?

Is there a guide on how to move from spike to another processor? (Presumably changing print/finish routines or some such)

Best,

-Dan

On Oct 5, 2023, at 5:38 PM, Jerin Joy <j...@rivosinc.com> wrote:



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[Jerin Joy]

Thanks Dan.

I may have missed it, but are there capabilities to trigger interrupts in diags?

This should show up in a future PR. 

Is there a guide on how to move from spike to another processor? (Presumably changing print/finish routines or some such)

Yes, the change should primarily be in the end of sim code in src/public/end.machine.S:

https://github.com/rivosinc/JumpStart/blob/main/src/public/end.machine.S#L69

Right now it runs the spike end of sim sequence.

Jerin