RISC-V tool chain support for MMU-less RISC-V core

[harsha kondajji]

Hello,

 Does the RISC-V tool chain provide support to build Linux image for MMU less RISC-V core.

Thanks & Regards,

Harsha

[Hesham Almatary]

Hi,

The tool chain has nothing to do with MMU. Operating systems (including Linux) are managing the MMU. The RISC-V Linux port and bbl handle MMU setup and configuration.

There's a Linux project called uclinux that tries to work with no MMU, but this one is not ported to RISC-V.

Regards, 
Hesham

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[Jamey Hicks]

Hi Harsha,

Other no-mmu architectures are now supported in the mainstream Linux kernel, but there is currently no Linux kernel support for no-MMU RISC-V cores.

These architectures used FLT/FLAT shared library format, which does require toolchain support. I do not know the difference between FLAT and ELF, though.

Regards,

Jamey

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[Palmer Dabbelt]

We don't support MMU-less systems because we're not building them, but we
wouldn't be opposed to patches that add support. I think the toolchain work
required would be pretty lightweight, and since the toolchain is stable it
would be a reasonable time to work on this. The supervisor spec hasn't been
finalized so it might be more of a mess to add OS support. The supervisor
spec should be finishing up soon, though.

We had a student looking into a FreeRTOS port, but it looks like he's
disappeared so it probably isn't being worked on.

>> <https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/CAFout0WdT9jxp_eTAoW__QGGiq6UJsdjvz4Gcq3gRQbr5z7kYA%40mail.gmail.com?utm_medium=email&utm_source=footer>
>> .
>>

[Hesham Almatary]

Hi Harrsha,

If you are just looking for a RISC-V OS with no MMU, there's an RTEMS (RTOS) port that I worked on last year [1, 2]. It doesn't use MMU, and runs in Machine mode (it does run in S-Mode only when running with seL4, but this is another BSP/implementation). However it is most likely outdated now because of the tool chain and specification changes (privilege instructions, start address, timer, vectors, etc).

[1] http://heshamelmatary.blogspot.com.au/2015/12/rtems-port-for-risc-v-withwithout-sel4.html
[2] https://github.com/heshamelmatary/rtems-riscv

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[harsha kondajji]

Hello,

Thanks a lot for the information.

Can you also provide information on when will the final supervisor spec be available.

Thanks & Regards,

Harsha

[harsha kondajji]

Hi Hesham,

Thanks for the information. Will look into the links you have shared.

Thanks & Regards,

Harsha