Linker file

Sharat Kumar

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Feb 16, 2017, 5:30:05 PM2/16/17

to RISC-V SW Dev

Hello All,

I am starting to explore RISC-V. I am trying to compile in accord to our soc setup.

My run command is.

riscv64-unknown-elf-gcc -g <path>/max_power.c -I <some_path> -o max_power.o -L

It goes fine and generates .o file and then I generate LST and hex file from that. But the generated code is at an offset of

max_power.o: file format elf64-littleriscv

Disassembly of section .text:

00000000000100b0 <_start>:

....

My ROM is at 0x0. For these we used to pass Linker files to show the locations of ROM/RAM.

An example below.

INCLUDE "<>"

MEMORY

{

FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K */

RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0xFFE0 /* 64K (-32 bytes) */

}

These generally come with the MCU that we used. How do I get these files for RISC-V? If someone can send me an example which worked for them, it will be very helpful.

Thank you

John Leidel

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Feb 16, 2017, 5:38:13 PM2/16/17

to Sharat Kumar, RISC-V SW Dev

Sharat, you can modify the default linker script with your preferred starting address for text. The riscv-tools package does this a fair amount. I believe the current RISC-V linker script is located at $RISCV/riscv64-unknown-elf/lib/riscv.ld. For examples of other linker scripts, search for *.ld in the riscv-tools repository.

cheers

john

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John Leidel

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Feb 16, 2017, 5:38:55 PM2/16/17

to Sharat Kumar, RISC-V SW Dev

...slight correction, search for the linker scripts in the riscv-tests repository.

On Thu, Feb 16, 2017 at 4:38 PM, John Leidel <john....@gmail.com> wrote:

Sharat, you can modify the default linker script with your preferred starting address for text. The riscv-tools package does this a fair amount. I believe the current RISC-V linker script is located at $RISCV/riscv64-unknown-elf/lib/riscv.ld. For examples of other linker scripts, search for *.ld in the riscv-tools repository.

cheers
john

On Thu, Feb 16, 2017 at 4:30 PM, Sharat Kumar <sharatk...@gmail.com> wrote:

Hello All,

I am starting to explore RISC-V. I am trying to compile in accord to our soc setup.

My run command is.

riscv64-unknown-elf-gcc -g <path>/max_power.c -I <some_path> -o max_power.o -L

It goes fine and generates .o file and then I generate LST and hex file from that. But the generated code is at an offset of

max_power.o: file format elf64-littleriscv
Disassembly of section .text:
00000000000100b0 <_start>:
....

My ROM is at 0x0. For these we used to pass Linker files to show the locations of ROM/RAM.

An example below.

INCLUDE "<>"
MEMORY
{
FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0xFFE0 /* 64K (-32 bytes) */
}

These generally come with the MCU that we used. How do I get these files for RISC-V? If someone can send me an example which worked for them, it will be very helpful.

Thank you

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Sharat Kumar

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Feb 16, 2017, 5:44:50 PM2/16/17

to John Leidel, RISC-V SW Dev

Thanks John. I will try your suggestion.

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Sharat Kumar

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Feb 21, 2017, 3:52:04 PM2/21/17

to John Leidel, RISC-V SW Dev

I added a link.ld file.

/////

OUTPUT_ARCH( "riscv" )

MEMORY

{

FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x10000 /* 64K */

RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0xFFE0 /* 64K (-32 bytes) */

}

/////

It spewed errors like this.

/tools/site/linux/riscv_toolchain/20170126/lib/gcc/riscv64-unknown-elf/6.1.0/../../../../riscv64-unknown-elf/lib/crt0.o: In function `.L0 ':

/export/tmp2/wroberts/build/riscv_tmp/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/libgloss/riscv/crt0.S:9: undefined reference to `_gp'

/export/tmp2/wroberts/build/riscv_tmp/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/libgloss/riscv/crt0.S:13: undefined reference to `_edata'

/export/tmp2/wroberts/build/riscv_tmp/riscv-tools/riscv-gnu-toolchain/build/src/newlib-gcc/libgloss/riscv/crt0.S:14: undefined reference to `_end'

collect2: error: ld returned 1 exit status

That was because my previous proc had "SECTIONS" tab in that.

Not knowing any better, I copied over sections from some link.ld file I found in risc-tests.

SECTIONS

{

/* text: test code section */

. = 0x80000000;

.text.init : { crt.o(.text) }

.tohost ALIGN(0x1000) : { *(.tohost) }

.text : { *(.text) }

/* data segment */

.data : { *(.data) }

.sdata : {

_gp = . + 0x800;

*(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)

*(.sdata .sdata.* .gnu.linkonce.s.*)

}

/* bss segment */

.sbss : {

*(.sbss .sbss.* .gnu.linkonce.sb.*)

*(.scommon)

}

.bss : { *(.bss) }

/* thread-local data segment */

.tdata :

{

_tls_data = .;

crt.o(.tdata.begin)

*(.tdata)

crt.o(.tdata.end)

}

.tbss :

{

*(.tbss)

crt.o(.tbss.end)

}

/* End of uninitalized data segement */

_end = .;

}

And then it returned

/tools/site/linux/riscv_toolchain/20170126/lib/gcc/riscv64-unknown-elf/6.1.0/../../../../riscv64-unknown-elf/bin/ld: cannot find crt.o

I am sorry I do not understand software very much to debug this quickly and hence I seek your help. Other PROCs usually come with all these infrastructures(linker files). Is there something which I can just adapt from?

Thanks in advance

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Bruce Hoult

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Feb 21, 2017, 4:00:06 PM2/21/17

to Sharat Kumar, John Leidel, RISC-V SW Dev

On Tue, Feb 21, 2017 at 11:52 PM, Sharat Kumar <sharatk...@gmail.com> wrote:

I am sorry I do not understand software very much to debug this quickly and hence I seek your help. Other PROCs usually come with all these infrastructures(linker files). Is there something which I can just adapt from?

What hardware do you have?

RISC-V is an instruction set, not a processor. Whatever hardware you have should indeed come with appropriate linker scripts.

The only shipping and purchasable RISC-V hardware I'm aware of is the HiFive1 board, which does indeed come with a suitably configured toolchain in the freedom-e-sdk (which is shared with a FPGA version of the same design). The flash and RAM for those is at very different locations to what you're setting up.

Sharat Kumar

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Feb 21, 2017, 7:32:40 PM2/21/17

to Bruce Hoult, John Leidel, RISC-V SW Dev

Hi Bruce,

Sorry if I misled with my question. I am seeking a template linker file, to which i can fill in rom/ram location.

Right now I am just trying to compile my driver firmware with hex/lst file appropriately created with the locations I specify.

Shilpa

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Sep 13, 2020, 4:12:20 AM9/13/20

to RISC-V SW Dev, Sharat Kumar, john.leidel, RISC-V SW Dev, Bruce Hoult

Hi Sharat,

Did you got the template for linker file?I am also having the same issue. If possible please share me linker file template..

Khem Raj

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Sep 14, 2020, 1:06:50 AM9/14/20

to Shilpa, RISC-V SW Dev, Sharat Kumar, john.leidel, Bruce Hoult

On 9/13/20 1:12 AM, Shilpa wrote:
> Hi Sharat,
> Did you got the template for linker file?I am also having the same
> issue. If possible please share me linker file template..
>

A good starting point may be dumping the internal linker script

<cross>-ld --verbose

will dump it.

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pEpkey.asc

Shilpa Gireesh

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Sep 14, 2020, 2:55:05 AM9/14/20

to Khem Raj, RISC-V SW Dev, Sharat Kumar

Thank You Khem and Sharat, the default linker script helped me with slight modification, I corrected my crt0.S file too.Now my problem was solved and getting the output.

Thank you for the support :-)

Thanks and Regards

Shilpa Das

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