Re: [sw-dev] Digest for sw-dev@groups.riscv.org - 1 update in 1 topic

[Robert Lipe]

Hardware Thread.

You're not the first to find this under documented, but it's trivial to find with a web search.

https://github.com/riscv/riscv-isa-manual/issues/822

It's a term relatively unique to RISC-V. Terms like CPU or core got fuzzy in recent times from things like hyper threading. AIUI, the term was used to not strictly require a complete execution unit, but any combination of magic that makes software think there are independent units. If you had a way to store eight register files (and probably a little extra state, such as whether it's WFI) and ran one opcide from each on each eighth opcode, you might convince software you had eight HARTs.

You'd die on a multithreaded benchmark or even real world use and the experience would be incredibly terrible, but I think that's approximately allowed. (That might be vaguely useful if you were simulating a chip on bigger metal or you chose something less extreme or you interleaved based on memory misses or something less dumb than round robin or such. 

On Sat, Mar 16, 2024, 8:25 PM <sw-...@groups.riscv.org> wrote:

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• Definition of "hart" - 1 Update

Definition of "hart"

Ahmed Juba <ahmed.j...@gmail.com>: Mar 16 01:32PM -0700 did you find out what is meant by "hart"? xD   On Saturday, November 18, 2017 at 1:26:41 AM UTC+2 tommy_...@hotmail.com wrote:

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