Re: [sw-dev] Digest for sw-dev@groups.riscv.org - 2 updates in 2 topics
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Robert Lipe
Apr 29, 2022, 2:09:57 AM4/29/22
to RISC-V SW Dev
I'm not familiar with that implementation, but I looked at the RISC-V code in that GitHub repo. That code is, more or less, the first implementation of every context (process or thread or interrupt or exception or coroutine) switch in about every project of this type - and often the last.
"Save all the registers" and "Restore all the registers" are pretty prescriptive and you can find this basic code in every mini-RTOS or "real" OS out there. It may need some attention for floating point, depending on the CPU and the application. That code is in the code I just linked if you need inspiration, thought you may be able to find versions with other licenses.
In RISC-V land, the 32 and 64 bit versions are usually so similar to each other that they use something like a STORE that's #defined to be sw or sd (word or double) with the obvious inverse for load but are otherwise identical.
Looking at the support and PR history of that project, I don't see any obvious history that screams that it's inherently "unstable". Indeed, I see zero references in those areas to RISC-V at all. It looks like the program would benefit from a good test suite (admittedly non-trivial to do portably, but far from impossible) but there's not a lot of complaints from the users.
If you perceive stability issues in this project, I'd suggest you submit a test case and work with the authors of this code to identify and correct any issues. It looks approximately "right".
RJL
"Save all the registers" and "Restore all the registers" are pretty prescriptive and you can find this basic code in every mini-RTOS or "real" OS out there. It may need some attention for floating point, depending on the CPU and the application. That code is in the code I just linked if you need inspiration, thought you may be able to find versions with other licenses.
In RISC-V land, the 32 and 64 bit versions are usually so similar to each other that they use something like a STORE that's #defined to be sw or sd (word or double) with the obvious inverse for load but are otherwise identical.
Looking at the support and PR history of that project, I don't see any obvious history that screams that it's inherently "unstable". Indeed, I see zero references in those areas to RISC-V at all. It looks like the program would benefit from a good test suite (admittedly non-trivial to do portably, but far from impossible) but there's not a lot of complaints from the users.
If you perceive stability issues in this project, I'd suggest you submit a test case and work with the authors of this code to identify and correct any issues. It looks approximately "right".
RJL
On Thu, Apr 28, 2022 at 8:25 PM <sw-...@groups.riscv.org> wrote:
- Support for Go lang for RISCV 32 bit - 1 Update
- libucontext support for riscv - 1 Update
Yan Titarenko <yantit...@gmail.com>: Apr 28 04:05PM +0300
Please check gollvm
Rob Wynden <rwy...@gmail.com>: Apr 27 11:36PM -0700
Hello,
There is a very popular open source library available for porting legacy
software that is dependent on ucontext.h.
The github repo is available here:
https://github.com/kaniini/libucontext
This codebase DOES attempt to support RiscV5. However, the code is
unstable.
Do you know of alternative implementations of ucontext.h (makecontext,
swapcontext, setcontext and getcontext) for RiscV5?
Thanks.
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Rob Wynden
May 4, 2022, 8:07:10 PM5/4/22
to RISC-V SW Dev, rober...@gmail.com
Thank you.
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