Why are VPN and PPN of different size in Virtual Memory System ?

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Vincent Siles

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Apr 26, 2018, 5:06:47 AM4/26/18
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Hi !
I'm used to write bare metal code, with MMU on ARM systems, and I'm starting to learn about risc-v architecture, so I started to read the parts of the privileged specification I'm more familiar with: the Virtual Memory System.

I was surprised to see that the size of virtual address and physical address don't match (a bit like in ARM LPAE design). For example in Sv32, VPN[1] is 10 bits but PPN[1] is 12 bits.

Then in the 'Virtual Address Translation Process', the last part is to set PPN[1] = VPN[1].
Then why the difference in size ?

It seems to be the same in Sv39 and Sv48.

What are the motivation between such design and how could the additional bits be used in the design of an OS MMU ?

Best regards,
Vincent

Paul Miranda

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Apr 26, 2018, 10:23:32 PM4/26/18
to RISC-V SW Dev, vincen...@ens-lyon.org
If I understand the RV definition, the size of each successive page is driven by how many page table entries fit in the smallest page.
So in sv32, a 2^12 byte page can hold 2^10 2^2-byte entries.
In sv39 and sv48, a 2^12 byte page can hold 2^9 2^3 byte entries.

ron minnich

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Apr 26, 2018, 11:25:24 PM4/26/18
to Vincent Siles, sw-...@groups.riscv.org
On Thu, Apr 26, 2018 at 2:06 AM Vincent Siles <vincen...@ens-lyon.org> wrote:
Hi !
I'm used to write bare metal code, with MMU on ARM systems, and I'm starting to learn about risc-v architecture, so I started to read the parts of the privileged specification I'm more familiar with: the Virtual Memory System.

I was surprised to see that the size of virtual address and physical address don't match (a bit like in ARM LPAE design). For example in Sv32, VPN[1] is 10 bits but PPN[1] is 12 bits.



the address is word-aligned in the PTE, so you can dispense with the low order 2 bits, hence 10 bits. It's a really good idea, it buys 2 more bits, unlike x86 which wastes them.

ron 

Vincent Siles

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Apr 27, 2018, 1:33:58 AM4/27/18
to ron minnich, sw-...@groups.riscv.org
I get the 10 bits part, but then why is PPN[0] 10 bits and PPN[1] 12 bits when both VPN[0] and VPN[1] are 10 bits ?
I think it is like ARM's LPAE idea, to allow accessing more RAM even with only 32 bit of virtual addresses, but I don't understand why this situation (physaddr > virtaddr) remains in the two other modes.

Christoph Hellwig

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Apr 27, 2018, 1:38:21 AM4/27/18
to Vincent Siles, ron minnich, sw-...@groups.riscv.org
On Fri, Apr 27, 2018 at 07:33:55AM +0200, Vincent Siles wrote:
> I get the 10 bits part, but then why is PPN[0] 10 bits and PPN[1] 12 bits
> when both VPN[0] and VPN[1] are 10 bits ?
> I think it is like ARM's LPAE idea, to allow accessing more RAM even with
> only 32 bit of virtual addresses, but I don't understand why this situation
> (physaddr > virtaddr) remains in the two other modes.

Exactly. Same as x86 PAE or arm LPAE or whatever the mips version is
called. 4GB is very low in terms of physical memory even for a 32-bit
CPU these days, while you can probably do with 4G virtual, although
it would be a lot less painful if we had a full supervisor/user
address space split (shameless plug :))

Vincent Siles

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Apr 27, 2018, 2:01:43 AM4/27/18
to Christoph Hellwig, ron minnich, sw-...@groups.riscv.org
Ok, I got it, thanks !
Don't spoil too much yet, I didnt' reach the part where I'm looking for my user vs kernel virtual space :D

Have a nice day !
V.


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