Adding vector intrinsic to Riscv gcc

[hameeza ahmed]

Hello

I am trying to add intrinsic in gcc riscv. I made following changes but when i run c code using new intrinsic its not generating assembly.

What am I missing? What further changes are needed? please guide.

in riscv-vector-builtins-functions.def

 DEF_RVV_FUNCTION(vadd_xcal, vadd_xcal, (3, VITER(VI, signed), VATTR(0, VI, signed), VATTR(0, VI, signed)), pat_mask_tail, pred_all, OP_vv | OP_vx)

in riscv-vector-builtins-functions.cc

 rtx
  vadd_xcal::expand (const function_instance &instance, tree exp, rtx target) const
   {
          machine_mode mode = TYPE_MODE (TREE_TYPE (exp));
            enum insn_code icode;
             if (instance.get_operation () == OP_vv)
                       icode = code_for_vadd_xcalerium_vv (mode);
             else
                     icode = code_for_v_vx (UNSPEC_VADD_XCAL, mode);
             return expand_builtin_insn (icode, exp, target, instance);
           }

in riscv-vector-builtins-functions.h

class vadd_xcal : public binop
 {
 public:
  // use the same construction function as the binop
   using binop::binop;
 virtual rtx expand (const function_instance &, tree, rtx) const override;
  };

in vector.md

;; Vector-scalar Integer add: vadd.vx

;; Optimize the const vector that all elements

  ;; are 5-bit signed immediate value with

  ;; vadd.vi.

  (define_insn "@vadd_xcal<mode>_vx_internal"

    [(set (match_operand:VI 0 "register_operand"              "=vd,vd,vd,vd,  vr,vr,vr,vr")

   (unspec:VI

     [(unspec:VI

      [(match_operand:<VM> 1 "vector_reg_or_const0_operand" "vm,vm,vm,vm,   J,J,J,J")

      (plus:VI

          (match_operand:VI 3 "register_operand"             "vr,vr,vr,vr,   vr,vr,vr,vr")

        (vec_duplicate:VI

          (match_operand:<VSUB> 4 "reg_or_simm5_operand"   "r,r,Ws5,Ws5,   r,r,Ws5,Ws5")))

      (match_operand:VI 2 "vector_reg_or_const0_operand"   "0,J,0,J,       0,J,0,J")

      ] UNSPEC_SELECT)

     (match_operand 5 "p_reg_or_const_csr_operand"          "rK,rK,rK,rK,   rK,rK,rK,rK")

    (match_operand 6 "const_int_operand")

      (reg:SI VL_REGNUM)

     (reg:SI VTYPE_REGNUM)] UNSPEC_RVV))

    (clobber (match_operand 7 "pmode_register_operand" "=&r,&r,&r,&r,&r,&r,&r,&r"))]

    "TARGET_VECTOR"

    "@

   vadd_xcal.vx\t%0,%3,%4,%1.t

   vadd_xcal.vx\t%0,%3,%4,%1.t

   vadd_xcal.vi\t%0,%3,%4,%1.t

     vadd_xcal.vi\t%0,%3,%4,%1.t

     vadd_xcal.vx\t%0,%3,%4

     vadd_xcal.vx\t%0,%3,%4

     vadd_xcal.vi\t%0,%3,%4

   vadd_xcal.vi\t%0,%3,%4"

    [(set_attr "type" "varith")

    (set_attr "mode" "<MODE>")])

(define_insn "@vadd_xcal<mode>_vx_32bit"

    [(set (match_operand:V64BITI 0 "register_operand"             "=vd,vd,vd,vd,vr,vr,vr,vr")

    (unspec:V64BITI

    [(unspec:V64BITI

     [(unspec:V64BITI

        [(match_operand:<VM> 1 "vector_reg_or_const0_operand"     "vm,vm,vm,vm,J,J,J,J")

      (plus:V64BITI

        (match_operand:V64BITI 3 "register_operand"            "vr,vr,vr,vr,vr,vr,vr,vr")

         (vec_duplicate:V64BITI

           (sign_extend:<VSUB>

              (match_operand:SI 4 "reg_or_simm5_operand"         "r,Ws5,r,Ws5,r,Ws5,r,Ws5"))))

      (match_operand:V64BITI 2 "vector_reg_or_const0_operand"  "0,0,J,J,0,0,J,J")

        ] UNSPEC_SELECT)

     (match_operand:SI 5 "csr_operand"                          "rK,rK,rK,rK,rK,rK,rK,rK")

      (match_operand:SI 6 "const_int_operand")

      (reg:SI VL_REGNUM)

     (reg:SI VTYPE_REGNUM)] UNSPEC_RVV))

     (clobber (match_operand 7 "pmode_register_operand" "=&r,&r,&r,&r,&r,&r,&r,&r"))]

    "TARGET_VECTOR"

      "@

      vadd_xcal.vx\t%0,%3,%4,%1.t

   vadd_xcal.vi\t%0,%3,%4,%1.t

     vadd_xcal.vx\t%0,%3,%4,%1.t

     vadd_xcal.vi\t%0,%3,%4,%1.t

   vadd_xcal.vx\t%0,%3,%4

    vadd_xcal.vi\t%0,%3,%4

    vadd_xcal.vx\t%0,%3,%4

    vadd_xcal.vi\t%0,%3,%4"

    [(set_attr "type" "varith")

   (set_attr "mode" "<MODE>")])

in vector-iterators.md

   (UNSPEC_VADD "add") (UNSPEC_VADD_XCALERIUM "add_xcal")......

[hameeza ahmed]

Please guide. I am stuck in this. Please

[Tommy Murphy]

Perhaps it would be useful to look at previous vector intrinsic patches contributed to GCC and use those as a guide? For example:

* https://www.mail-archive.com/gcc-p...@gcc.gnu.org/msg330361.html 

[hameeza ahmed]

I have followed above mentioned patch to add intrinsic. I have added vandndummy intrinsic. It is compiled successfully. But in assembly its not generating vandndummy instruction but its generating vandn instruction as attached below.

# test/test.c:36:     vc = __riscv_vandndummy_vv_u32m2 (va, vb, vl);
 79     .loc 1 36 10 is_stmt 0
 80     vandn.vv    v2,v2,v6    # _3, va, vb,

Please guide what am I missing?

Thank You