LLVM for RISC-V

[Alexandra Larossa]

Hello, all this is Alex I'm a newbie in the compiler world I'm trying to setup LLVM for RISC-V environment first, anybody of you can help me in setting up the environment of llvm for RISC-V and generating first assembly code for RISC-V through LLVM or any documentation available for setting up the environment

Looking forward to hear from you.

cheers,

Alex

[Wei Wu (吴伟)]

Hi Alexandra,

Glad to help. Mingjie Xing is working on RISC-V Vector Ext in LLVM. I cc'd him on this email. He may provide some hints soon.

Welcome to the RISC-V community!

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Best wishes,
Wei Wu (吴伟)

[Khem Raj]

Hi Alexandra

If you are interested in cross compilers for Linux using clang/llvm
you can use meta-clang with yocto/openembedded

https://github.com/kraj/meta-clang/blob/master/README.md

for riscv you would also add meta-riscv

https://github.com/riscv/meta-riscv/blob/master/README.md

if you want full in one go then use yoe distro

https://github.com/YoeDistro/yoe-distro/blob/master/README.md

. ./qemuriscv64-envsetup.sh

in conf/local.conf add

TOOLCHAIN ?= "clang"
CLANGSDK = "1"

to use clang as the compiler.

Thanks
-Khem

[Alexandra Larossa]

Thank you so much Wei Wu and Khem for this overwhelming response

On Tue, Dec 15, 2020 at 7:27 PM Paidipally Kranthi <paidipall...@gmail.com> wrote:

hi All,

I am new to RVV and tried executing simple vector ADD on top of RVV9.x. Compilation and build (RV32IMV option used) is fine.

When i executed binary I get illegal instruction

core   0: 0xffffffff80002348 (0xfd1ff0ef) jal     pc - 0x30

core   0: 0xffffffff80002318 (0x0285c257) vadd.vx v4, v8, a1

core   0: exception trap_illegal_instruction, epc 0xffffffff80002318

core   0:           tval 0x000000000285c257

I am not sure how to debug this. how would build succesful if instruction itself is not present or illegal?

Any insight please? Highly appreciate help

Thank you,