What does 1: mean in riscv-test.h

[Jimmy Situ]

Hello all,

I was reading the source code of RISC-V test pattern.
And there is a macro define in riscv-test.h,
I just want to know what does 1: mean in this code. Anyone could help? Thanks.

I paste the macro below

#define RVTEST_CODE_BEGIN                                               \
        .section .text.init;                                            \
        .align  6;                                                      \
        .weak stvec_handler;                                            \
        .weak mtvec_handler;                                            \
        .globl _start;                                                  \
_start:                                                                 \
        /* reset vector */                                              \
        j reset_vector;                                                 \
        .align 2;                                                       \
trap_vector:                                                            \
        /* test whether the test came from pass/fail */                 \
        csrr t5, mcause;                                                \
        li t6, CAUSE_USER_ECALL;                                        \
        beq t5, t6, write_tohost;                                       \
        li t6, CAUSE_SUPERVISOR_ECALL;                                  \
        beq t5, t6, write_tohost;                                       \
        li t6, CAUSE_MACHINE_ECALL;                                     \
        beq t5, t6, write_tohost;                                       \
        /* if an mtvec_handler is defined, jump to it */                \
        la t5, mtvec_handler;                                           \
        beqz t5, 1f;                                                    \
        jr t5;                                                          \
        /* was it an interrupt or an exception? */                      \
  1:    csrr t5, mcause;                                                \
        bgez t5, handle_exception;                                      \
        INTERRUPT_HANDLER;                                              \
handle_exception:                                                       \
        /* we don't know how to handle whatever the exception was */    \
  other_exception:                                                      \
        /* some unhandlable exception occurred */                       \
  1:    ori TESTNUM, TESTNUM, 1337;                                     \
  write_tohost:                                                         \
        sw TESTNUM, tohost, t5;                                         \
        j write_tohost;                                                 \
reset_vector:                                                           \
        RISCV_MULTICORE_DISABLE;                                        \
        CHECK_XLEN;                                                     \
        li TESTNUM, 0;                                                  \
        la t0, trap_vector;                                             \
        csrw mtvec, t0;                                                 \
        csrwi medeleg, 0;                                               \
        csrwi mideleg, 0;                                               \
        csrwi mie, 0;                                                   \
        /* if an stvec_handler is defined, delegate exceptions to it */ \
        la t0, stvec_handler;                                           \
        beqz t0, 1f;                                                    \
        csrw stvec, t0;                                                 \
        li t0, (1 << CAUSE_FAULT_LOAD) |                                \
               (1 << CAUSE_FAULT_STORE) |                               \
               (1 << CAUSE_FAULT_FETCH) |                               \
               (1 << CAUSE_MISALIGNED_FETCH) |                          \
               (1 << CAUSE_USER_ECALL) |                                \
               (1 << CAUSE_BREAKPOINT);                                 \
        csrw medeleg, t0;                                               \
        csrr t1, medeleg;                                               \
        bne t0, t1, other_exception;                                    \
1:      csrwi mstatus, 0;                                               \
        init;                                                           \
        EXTRA_INIT;                                                     \
        EXTRA_INIT_TIMER;                                               \
        la t0, 1f;                                                      \
        csrw mepc, t0;                                                  \
        csrr a0, mhartid;                                               \
        mret;                                                           \
1:

[Stefan O'Rear]

On Sat, Sep 10, 2016 at 7:22 PM, Jimmy Situ <w...@jimmystone.cn> wrote:
> Hello all,
>
> I was reading the source code of RISC-V test pattern.
> And there is a macro define in riscv-test.h,
> I just want to know what does 1: mean in this code. Anyone could help?
> Thanks.
>
> I paste the macro below

Those are 'gas' local labels; see "Local Labels" in
https://sourceware.org/binutils/docs/as/Symbol-Names.html#Symbol-Names

-s

[Christopher Celio]

"1:" is a local label. It allows the assembly writer to use unique labels for branch targets.

https://sourceware.org/binutils/docs/as/Symbol-Names.html

-Chris

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