tlb flush

[vithurson subasharan]

In a pipelined architecture , if the address of root page table (ppn in satp reg) is updated while virtual memory   is active, should implementation flush the tlb's without even waiting for sfence vma to be executed?

thanks.

-regards

-Vithurson

[Andrew Waterman]

On Wed, Feb 20, 2019 at 8:22 AM vithurson subasharan <vith...@gmail.com> wrote:

In a pipelined architecture , if the address of root page table (ppn in satp reg) is updated while virtual memory   is active, should implementation flush the tlb's without even waiting for sfence vma to be executed?

thanks.

In a conventional microarchitecture, you don’t need to flush the TLB in this situation. Software needs to explicitly use an SFENCE.VMA if mappings have changed. This design is necessary to support ASIDs: if every satp write caused a TLB flush, having ASIDs would not improve performance.

-regards

-Vithurson

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[vithurson subasharan]

Sfence-vma should flush the pipeline also? 

[Andrew Waterman]

On Wed, Feb 20, 2019 at 11:06 AM vithurson subasharan <vith...@gmail.com> wrote:

Sfence-vma should flush the pipeline also? 

Yeah.

[vithurson subasharan]

does current riscv-linux require asid to be implemented?

[Andrew Waterman]

On Fri, Feb 22, 2019 at 4:52 AM vithurson subasharan <vith...@gmail.com> wrote:

does current riscv-linux require asid to be implemented?

No. When ASID support is eventually added to RISC-V Linux, it will be optional.

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