LR/SC order of execution?

[premjithav]

When we are running a test program we have gone through following scenario:

lr.d ---address--0x80004000

lr.w--address---0x80004000

sc.d--address--0x80004000

sc.w--address--0x80004000

as per the specification sc.d should fail or pass? In spike simulator it is passing. Is it free adopt the implementation or any conditions is there?

[Radim Krčmář]

2025-08-19T04:46:26-07:00, premjithav <premj...@gmail.com>:

> When we are running a test program we have gone through following scenario:
>
> lr.d ---address--0x80004000
>
> lr.w--address---0x80004000
>
> sc.d--address--0x80004000
>
> sc.w--address--0x80004000

(The second sc.w always fails, and the first lr.d has no effect.)

> as per the specification sc.d should fail or pass? In spike simulator it is
> passing.

This program can be simplified to to:

lr.w--address---0x80004000
sc.d--address--0x80004000

sc.d can fail or succeed in this case, depending on the implementation.

--- Long explanation:
The reservation set created by lr.w can be, e.g., a cacheline:

An implementation can register an arbitrarily large reservation set on
each LR, provided the reservation set includes all bytes of the
addressed data word or doubleword.

The manual points out that it is the reservation set, not the original
lr that matters when figuring out whether sc must fail:

Note this LR might have had a different effective address and data
size, but reserved the SC’s address as part of the reservation set.

Software must not depend on this succeeding, though, because the
reservation set defined by lr.w can be only "w", and:

The SC must fail if the address is not within the reservation set of
the most recent LR in program order.

> Is it free adopt the implementation or any conditions is there?

Spike is within the constraints of the Zalrsc chapter.