getauxval(AT_HWCAP): Vector Extension 1.0

[Mathieu Malaterre]

Hi there,

I am trying to detect V-extension on RISC-V arch. For some reason I cannot find anything in `arch/riscv/include/asm/hwcap.h` (linux git/master).

Looking at arm arch, everything is there. For example:

% grep HWCAP_NEON arch/arm/include/uapi/asm/hwcap.h
#define HWCAP_NEON      (1 << 12)

which can be queried by a simple getauxval(AT_HWCAP).

What would be the equivalent on RISC-V/Linux ?

[Tommy Murphy]

Isn't it via $misa.V?

See the V extension spec

https://github.com/riscv/riscv-v-spec/releases/tag/v1.0

And the privileged spec:

https://riscv.org/technical/specifications/ 

[Mathieu Malaterre]

Hi Tommy

Thanks for the speedy help. Any suggestion for the following:

$ gcc -g -Wall -Wextra misa.c && ./a.out
Illegal instruction

where:


$ cat misa.c
#include <stdint.h>
#include <stdio.h>

#if __riscv_xlen==32
typedef uint32_t uint_xlen_t;
#elif __riscv_xlen==64
typedef uint64_t uint_xlen_t;
#else
#error "Unknown XLEN"
#endif

#if !defined(__riscv_zicsr)
#error "-march must include zicsr to access CSRs"
#endif

static inline uint_xlen_t csr_read_misa(void) {
uint_xlen_t value;
__asm__ volatile ("csrr %0, misa"
: "=r" (value) /* output : register */
: /* input : none */
: /* clobbers: none */);
return value;
}

int main()
{
uint_xlen_t misa = csr_read_misa() ;
printf("%lu\n", misa );
}

Thanks again
--
Mathieu

[Tommy Murphy]

Is this on Linux on RISC-V?

If so, then it's probably because a Linux user process (presumably running in RISC-V U mode) can't read the M (machine) mode $misa CSR and will trigger a fault?

Maybe something like the SBI allows indirect access by user mode to $misa? Or maybe it doesn't on grounds of security?

I'm less au fait with Linux and related layers on RISC-V than with bare metal/RTOS unfortunately.

[Tommy Murphy]

From the privileged spec:

"We require that lower privilege levels execute environment calls instead of reading CPU

registers to determine features available at each privilege level. This enables virtualization layers

to alter the ISA observed at any level, and supports a much richer command interface without

burdening hardware designs."

[Valentin Nechayev]

Fri, Sep 02, 2022 at 11:05:09, tommy_murphy wrote about "Re: [sw-dev] getauxval(AT_HWCAP): Vector Extension 1.0":

> Is this on Linux on RISC-V?
> If so, then it's probably because a Linux user process (presumably running in RISC-V U mode) can't read the M (machine) mode $misa CSR and will trigger a fault?

So it is returning to the original question - what is the nominal way to
detect an extension presence from Linux userland.

Regarding "V", Iʼd notice that its multi-parameter nature require a
separate definition, not a single flag...


-netch-

[Tommy Murphy]

I had a quick look at OpenSBI but can't see anything obvious there for detecting ISA extensions (and there could be reason that this is not facilitated?):

https://github.com/riscv-software-src/opensbi

Perhaps this discussion is of some interest here?

https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/9wzcKYQfdZo