RISC-V Port Merged to Linux

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Palmer Dabbelt

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Nov 15, 2017, 2:51:55 PM11/15/17
to sw-...@groups.riscv.org, alb...@sifive.com, Arnd Bergmann
The RISC-V port was just merged to Linux a few minutes ago. This means we will
be in the 4.15 release, which should be out about 10 weeks from last Sunday.
As soon as the tarballs are created, the RISC-V Linux ABI will be stable, and
since we'll ideally be in a glibc release that comes out soon after that we'll
be fully ABI stable by early in February.

While this is a big accomplishment, it does mean we now have a clock on sorting
out the user-visible ABI issues. The current problems I know of are:

* Signal registers are mismatched, these just need to be sanitized.
* We're going to add some VDSO entries.
* We need an i-cache fence system call.

I'll be fixing these up ASAP, along with a handful of other comments and
fallout from the merge. If anyone else knows about any ABI weirdness in RISC-V
Linux land then speak up soon -- if you don't, then we'll be stuck with it
forever :).

If distribution people are interested in starting preliminary work, I've got
backports of Linux and glibc tagged in freedom-u-sdk, which will build and boot
a working kernel and userspace via "make sim". We won't be ready to actually
commit to a stable ABI for a bit, so it's not quite time to start releasing
binaries yet...

Thanks to everyone who has helped out. I'd specifically like to thank Albert
Ou, who is co-maintaining Linux with me, and Arnd Bergmann, who helped review
the port.

To anyone who is going to try out the port in its current state: good luck :).
The backports should be pretty solid!

John Leidel

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Nov 15, 2017, 2:53:03 PM11/15/17
to Palmer Dabbelt, RISC-V SW Dev, alb...@sifive.com, Arnd Bergmann
Palmer, congrats!! Thanks very much for helping to support the community with your diligent efforts.  



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Ted Speers

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Nov 15, 2017, 2:57:26 PM11/15/17
to Palmer Dabbelt, sw-...@groups.riscv.org, alb...@sifive.com, Arnd Bergmann
Nice!

Congrats to Palmer, Albert and Arnd on achieving the merge.


-----Original Message-----
From: Palmer Dabbelt [mailto:pal...@sifive.com]
Sent: Wednesday, November 15, 2017 11:52 AM
To: sw-...@groups.riscv.org
Cc: alb...@sifive.com; Arnd Bergmann <ar...@arndb.de>
Subject: [sw-dev] RISC-V Port Merged to Linux

EXTERNAL EMAIL

Michael Clark

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Nov 15, 2017, 3:00:35 PM11/15/17
to Palmer Dabbelt, alb...@sifive.com, Arnd Bergmann, RISC-V SW Dev, John Leidel
This is excellent news!

I think we will need some documentation on the riscv device tree eventually. Your --enable-print-device-tree patch to riscv-pk gets us most of the way there but it would be nice to have this documented somewhere. I’m going to see if I can get latest linux running in qemu… :-D
> To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/sw-dev/CAC6GRO8LhXKwYk%3DwTAnhYKvvsRJQZ5VNgbK1RkqpyfKQ1YMsUg%40mail.gmail.com.

Andrew Waterman

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Nov 15, 2017, 3:07:43 PM11/15/17
to Palmer Dabbelt, RISC-V SW Dev, Albert Ou, Arnd Bergmann
Awesome!

Krste Asanovic

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Nov 15, 2017, 3:10:07 PM11/15/17
to Palmer Dabbelt, RISC-V SW Dev, Albert Ou, Arnd Bergmann, Andrew Waterman
Wonderful news, a major RISC-V milestone!

Krste

Jeppe Johansen

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Nov 15, 2017, 3:44:13 PM11/15/17
to sw-...@groups.riscv.org
Great work!

Would the current state of the port support RV32I, or does it need the A
extension and/or 64 bit instructions?

Karsten Merker

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Nov 15, 2017, 4:07:41 PM11/15/17
to Jeppe Johansen, sw-...@groups.riscv.org
On Wed, Nov 15, 2017 at 09:44:10PM +0100, Jeppe Johansen wrote:

[RISC-V Linux port merged upstream]
> Would the current state of the port support RV32I, or does it
> need the A extension and/or 64 bit instructions?

The kernel code originally contained a syscall for emulating
atomic operations on systems without the A extension, but that
part has been rejected by upstream during the review phase, so
for the time being, the A extension is effectively mandatory.

Regards,
Karsten
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Bruce Hoult

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Nov 15, 2017, 4:26:15 PM11/15/17
to Palmer Dabbelt, RISC-V SW Dev, alb...@sifive.com, Arnd Bergmann
On Wed, Nov 15, 2017 at 10:51 PM, Palmer Dabbelt <pal...@sifive.com> wrote:
The RISC-V port was just merged to Linux a few minutes ago.  This means we will be in the 4.15 release, which should be out about 10 weeks from last Sunday.  As soon as the tarballs are created, the RISC-V Linux ABI will be stable, and since we'll ideally be in a glibc release that comes out soon after that we'll be fully ABI stable by early in February.

Fantastic!! Well done to all concerned.
 

Palmer Dabbelt

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Nov 15, 2017, 6:53:52 PM11/15/17
to mer...@debian.org, je...@j-software.dk, sw-...@groups.riscv.org
On Wed, 15 Nov 2017 13:07:38 PST (-0800), mer...@debian.org wrote:
> On Wed, Nov 15, 2017 at 09:44:10PM +0100, Jeppe Johansen wrote:
>
> [RISC-V Linux port merged upstream]
>> Would the current state of the port support RV32I, or does it
>> need the A extension and/or 64 bit instructions?
>
> The kernel code originally contained a syscall for emulating
> atomic operations on systems without the A extension, but that
> part has been rejected by upstream during the review phase, so
> for the time being, the A extension is effectively mandatory.

Yep, it's mandatory. If you're considering building a Linux-capable RISC-V
system right now, it'd probably be best to go with at least RV64IMAC (ideally
RV64GC), as that's going to get the most testing -- we expect non-multilib
distros will start with RV64GC.

When we upstream glibc, the plan is to have RV32IMAC, RV32GC, RV64IMAC, and
RV64GC as the default multilib set. We also expect that distros will also
follow suit here, as those are the only glibc targets we currently test
regularly.

We're open to expanding the number of ISAs we support in Linux land, but it
won't happen until we at least get the current set upstream. There's just too
many moving parts right now, we need some time to shake out issues with what
we've already got working. If there's a compelling reason to start supporting
more ISAs (ie, there's interesting hardware out there) then we can always add
them later. It's much harder to remove things.

Peter Ashenden

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Nov 15, 2017, 6:56:58 PM11/15/17
to sw-...@groups.riscv.org
Hi Palmer,

How much of the A-extension is used? Just LR/SC, or the AMO operations
also? Thanks.

PA
--
Peter Ashenden, CTO IC Design, ASTC

Daniel Lustig

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Nov 15, 2017, 7:04:36 PM11/15/17
to Krste Asanovic, Palmer Dabbelt, RISC-V SW Dev, Albert Ou, Arnd Bergmann, Andrew Waterman

+1, congratulations!

Dan


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Palmer Dabbelt

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Nov 15, 2017, 7:16:42 PM11/15/17
to peter.a...@astc-design.com, sw-...@groups.riscv.org
We make pretty much everything available to Linux

https://github.com/riscv/riscv-linux/blob/riscv-next/arch/riscv/include/asm/atomic.h
https://github.com/riscv/riscv-linux/blob/riscv-next/arch/riscv/include/asm/cmpxchg.h

though you might be able to get away with setting a bunch of Kconfig options
that remove most of those files. It's a bad idea (because we don't test it),
and it'll only work on single-hart systems, but it might be possible.

We also make all of them available glibc

https://github.com/riscv/riscv-glibc/blob/2f626de717a86be3a1fe39e779f0b179e13ccfbb/sysdeps/unix/sysv/linux/riscv/atomic-machine.h

and there's no way to build-time disable those because there's system call any
more. Of course, if you're on a single-hart system then you could always just
trap and emulate everything in M mode, then nobody would notice. It'd probably
be easier to get this right if you just implement A, though :).

Note that we'll only ever support non-A Linux systems with one hart, as there's
just no way to write sane multi-hart software without the A extension.
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mgi...@antmicro.com

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Nov 15, 2017, 9:43:55 PM11/15/17
to RISC-V SW Dev, peter.a...@astc-design.com, pal...@sifive.com
Congrats Palmer, Albert, Arnd & co, this is really huge news, definitely something we need to do a lot of marketing around! And right in time, a fantastic announcement for the upcoming Workshop.

Albert Ou

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Nov 15, 2017, 10:34:28 PM11/15/17
to sw-...@groups.riscv.org, Palmer Dabbelt, Quan Nguyen, Arnd Bergmann
Special thanks to Palmer for spearheading the upstreaming effort and to
Quan Nguyen, who started the port with me at Berkeley in 2012.
--
Albert Ou

Richard W.M. Jones

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Nov 16, 2017, 6:38:49 AM11/16/17
to Palmer Dabbelt, sw-...@groups.riscv.org, alb...@sifive.com, Arnd Bergmann
Great stuff.

From a Fedora point of view we're just waiting for glibc to go
upstream to start building things, so we should be able to start in
January or February (around FOSDEM time).

Rich.

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Jeshwanth Kumar N K

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Nov 16, 2017, 11:04:47 AM11/16/17
to RISC-V SW Dev, alb...@sifive.com, ar...@arndb.de, pal...@sifive.com
Congratulations.

If anybody wants to contribute for porting linux to RISC-V,  is there any board available to test ? or do we have qemu for RISC-V already?

How are you testing?

Palmer Dabbelt

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Nov 16, 2017, 11:14:42 AM11/16/17
to jeshku...@gmail.com, sw-...@groups.riscv.org, alb...@sifive.com, Arnd Bergmann
There are currently no ASIC-based dev boards available, but SiFive has
announced availability in Q1 2018. We do have FPGA-based development boards.
There are instructions on SiFive's website as to how to purchase one, currently
you'll need the VC707 to run Linux

https://dev.sifive.com/freedom-soc/evaluate/fpga/

Internally we have a handful of those boards that we test things on. The port
is reasonably solid: we can boot, mount disks via PCIe SATA controllers, and
run a handful of benchmarks/test suites, etc.

The QEMU port is out of date, but there's an active effort going on to update
it right now

https://github.com/riscv/riscv-qemu/pull/70

There's a handful of other ISA simulators available for RISC-V, you can build
and boot a kernel on Spike (our ISA golden model) by running "make sim" here:

https://github.com/sifive/freedom-u-sdk

It's the same kernel image that runs on the FPGA and will run on the ASIC based
boards.

Quan Minh Nguyen

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Nov 16, 2017, 2:46:52 PM11/16/17
to Albert Ou, sw-...@groups.riscv.org, Palmer Dabbelt, Arnd Bergmann
Congratulations to all for a job very well done! Hats off to Albert, co-conspirator extraordinaire, and to Arnd and Palmer for turning two undergrads' whimsical little project into something we couldn't have ever imagined when we started.

Here's Albert's first commit to riscv-linux from five years ago:

commit 786f6e84fac8736e255a1be1191e4ef10e012898
Author: Albert Ou
Date: Fri Jun 29 16:33:57 2012 -0700

Adding minimal subtree for the Linux/RISC-V port

The journey of a thousand lines of C begins with a single commit.

We instead ended up with 5,012 lines of C and 839 lines of assembly, according to David Wheeler's SLOCCount. Not bad.
Quan M. Nguyen
<q...@mit.edu>


Kao Quey-Liang

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Nov 24, 2017, 2:22:28 AM11/24/17
to RISC-V SW Dev, alb...@sifive.com, ar...@arndb.de, pal...@sifive.com
Hi Palmer,

Congradulations to you all for the accomplishment!  

Our software team in Andes Technology will start to contribute the RISC-V Linux port recenlty,
but we are still wondering which branch to be based on when formatting patch sets.
So the question is, which is the best branch that can ease the reviewing process?
Would it be __archive__? 4.14-rc8? or others?

Thanks!

Palmer Dabbelt於 2017年11月16日星期四 UTC+8上午3時51分55秒寫道:

John Leidel

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Nov 29, 2017, 7:34:31 PM11/29/17
to Kao Quey-Liang, RISC-V SW Dev, alb...@sifive.com, Arnd Bergmann, Palmer Dabbelt
Palmer (et al.), which riscv-tools branch/tag is suitable to build/test the Linux 4.15 rc1 tree?  

cheers
john 

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Jim Wilson

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Nov 29, 2017, 8:14:20 PM11/29/17
to John Leidel, Kao Quey-Liang, RISC-V SW Dev, alb...@sifive.com, Arnd Bergmann, Palmer Dabbelt
On Wed, Nov 29, 2017 at 4:34 PM, John Leidel <john....@gmail.com> wrote:
> Palmer (et al.), which riscv-tools branch/tag is suitable to build/test the
> Linux 4.15 rc1 tree?

The default branches you get from a riscv/riscv-gnu-toolchain checkout
on github should work. And if not, that is a bug that will have to be
quickly fixed.

Jim

John Leidel

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Nov 29, 2017, 8:24:04 PM11/29/17
to Jim Wilson, Kao Quey-Liang, RISC-V SW Dev, alb...@sifive.com, Arnd Bergmann, Palmer Dabbelt
Jim/Palmer, I had an issue in my cross compilation.  I believe I've shaken it out at this point.  The build appears to be rolling.  

cheers
john 
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