RISC-V Linux

[Michael Clark]

Hi All,

I’ve been having a poke around with the master branch of riscv-linux (4.6.2) and these are the issues I’ve found:

- external and timer interrupts are masked on boot - only software interrupts are currently enabled

- clock source is defined but timer interrupts are not being scheduled; this is at odds with the .config HZ setting

- console expects software interrupts although hardware sends external interrupts

- console and IPI can’t be distinguished from IPIs because the IPI signal number is not passed to the kernel

- linux sleeps waiting for timer interrupts - can’t see code that re-arms the one-shot timer

- console input can be enabled by changing sim to send software interrupts

- IRQ chip currently defines zero IRQs. PLIC needs some work

I’ve now made a reproducible recipe for building riscv-linux from source for anyone who wants to experiment with the master branch of the riscv-linux on an alternative sim to (Spike, riscv-qemu and RISCVEMU, ...). The only dependency is riscv-tools (well, the recipie will build busybox, riscv-linux and a modified BBL).

The model I am working on has a UART and a PLIC model similar to RISCVEMU. I have also made a fork of BBL that targets RV64G and uses UART for console IO (similar to the lowrisc untether BBL port). The BBL port has the bare minimum code for SBI stubs and to configure the page tables for a linux payload. Most of HTIF, Soft float emulation and proxy kernel have been removed as the goal was to see what was the minimum needed for kernel entry.

- https://github.com/michaeljclark/riscv-meta/

- https://github.com/michaeljclark/bbl-lite/

The sim has two sections added to the config string (see below) for UART version of BBL. The UART section contains a base address for an 8250-style UART (16550 without FIFO) for console IO. The HTIF section contains addresses of a memory mapped HTIF (the same addresses as RISCVEMU) which is used as a GPIO for the SBI shutdown call. Unlike Spike, the emulator does not look for symbols in the executable, but relies on their address being present in the config string. The UART frequency is ignored however a UART patch for BBL should probably add UART protocol parameters to the config string. I’ve documented the virtual hardware briefly here:

- https://github.com/michaeljclark/riscv-meta/blob/master/doc/src/mmio.md

If anyone is interested in trying this sim, while I don’t have binaries, I have a build script that depends only on riscv-tools. It needs both the riscv64-unknown-elf and riscv64-unknown-linux-gnu compilers (to latter to build busybox). There is a script that will build riscv-linux with a busybox initramfs embed in a bbl-lite payload:

- https://github.com/michaeljclark/riscv-meta/blob/master/scripts/bootstrap-linux.sh

The interrupt delivery logic is pretty easy to change (the master branch has a simple {M,S}-mode delivery that does not use the delegation registers). The model in master does not yet implement the {m,h,s}ideleg register for delegation:

- https://github.com/michaeljclark/riscv-meta/blob/master/src/emu/processor-priv-1.9.h

For anyone who already has the linux toolchain installed and RISCV environment variable set up on a Linux host, its possible to checkout riscv-meta and run the following to have linux booting in 15 or so minutes assuming a recent toolchain is present:

$ make -j4 && sudo make install

$ ./scripts/bootstrap-linux.sh

$ rv-sys build/bbl-lite/build/bbl

Regards,

Michael.

platform {
  vendor meta;
  arch anarch;
};
rtc {
  addr 0x40000000;
};
uart {
  addr 0x40003000;
};
htif {
  tohost 0x40008000;
  fromhost 0x40008008;
};
ram {
  0 {
    addr 0x80000000;
    size 0x40000000;
  };
};
core {
  0 {
    0 {
      isa rv64imafd;
      ipi 0x40001000;
      timecmp 0x40004000;
    };
  };
};