The following is the only info I could find:
RV32E and RV64E use the same instruction-set encoding as RV32I and RV64I respectively, except that only registers x0–x15 are provided. All encodings specifying the other registers x16–x31 are reserved.
This change requires a different calling convention and ABI. In particular, RV32E is only used with a soft-float calling convention. A new embedded ABI is under consideration that would work across RV32E and RV32I.
To be uber specific, my concern is the ability to compile programs which will run on a RV32I machine but which will only utilize the first 16 registers - hence the rationale to compile for RV32E. The reasoning for this is to support more performant translation to 16-register x86 CPUs running the RV32I VM.
To be even more specific to my own concerns, I have no interest in implementing any native float operations.
If RV32E programs ran on a RV32I machine will produce less deterministic results, I would like to be aware.