[PULL RFC] RISC-V Updates for the 4.19 Merge Window
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Palmer Dabbelt
Aug 13, 2018, 4:12:28 PM8/13/18
to Paul Walmsley, Atish Patra, Christoph Hellwig, sw-...@groups.riscv.org, linux...@lists.infradead.org
Below is the pull request I plan to submit on Wednesday morning. I'm planning
on using it as the basis of a riscv-linux-4.18 branch that consists of only
backports from the upstream kernel, which should make the RISC-V Linux
ecosystem a whole lot more stable.
I'm planning on submitting another PR with at least the icache flushing fixes
in it next week.
This is availiable as riscv-for-linus-4.19-mw0, or as riscv-linux-4.18 on
github. I've gone and marked that branch as rebase-proof under the speculation
that the PR gets merged, at which point riscv-linux-4.18 will be officially
rebase proof.
Thanks to everyone who helped out!
Here's the PR:
The following changes since commit 94710cac0ef4ee177a63b5227664b38c95bbf703:
Linux 4.18 (2018-08-12 13:41:04 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git tags/riscv-for-linus-4.19-mw0
for you to fetch changes up to 627672cf431b0379c07cc8d146f907cda6797222:
dt-bindings: interrupt-controller: SiFive Plaform Level Interrupt Controller (2018-08-13 09:39:11 -0700)
----------------------------------------------------------------
RISC-V Updates for the 4.19 Merge Window
This tag contains some major improvements to the RISC-V port, including
the necessary interrupt controller and timer support to actually make it
to userspace. Support for three devices has been added:
* Support for the ISA-mandated timers on RISC-V systems.
* Support for the ISA-mandated first-level interrupt controller on
RISC-V systems, which is handled as part of our core arch code because
it's very small and tightly tied to the ISA.
* Support for SiFive's platform-level interrupt controller, which talks
to the actual devices.
In addition to these new devices, there are a handful of cleanups all
over the RISC-V tree:
* Build fixes for various configurations
* A fix to the vDSO build's makefile so it respects CFLAGS.
* The addition of __lshrti3, a libgcc derived function necessary for
some 32-bit configurations.
* !SMP && PERF_EVENTS
* Cleanups to the arch code to remove the remnants of old versions of
the drivers that were just properly submitted.
* Some dead code from the timer driver, most of which wasn't ever
even compiled.
* Cleanups of some interrupt #defines, which are now local to the
interrupt handling code.
* Fixes to ptrace(), which while not being sufficient to fully make GDB
work are at least sufficient to get simple GDB tasks to work.
* Early printk support via RISC-V's architecturally mandated SBI console
device.
* A fix to our early debug trap handler to ensure it's always aligned.
These patches have all been through a fairly extensive review process,
but as this enables a whole pile of functionality (ie, userspace) I'm
confident we'll need to submit a few more patches. The only concrete
issues I know about are the sys_riscv_flush_icache patches, but as I
managed to screw those up on Friday I figured it'd be best to let them
bake another week.
This tag boots a Fedora root filesystem on QEMU's master branch for me,
and before this morning's rebase (from 4.18-rc8 to 4.18) it booted on
the HiFive Unleashed.
Thanks to Christoph Hellwig and the other guys at WD for getting the new
drivers in shape!
----------------------------------------------------------------
Alex Guo (1):
RISC-V: implement __lshrti3.
Atish Patra (1):
RISC-V: Fix !CONFIG_SMP compilation error
Christoph Hellwig (6):
RISC-V: remove timer leftovers
RISC-V: simplify software interrupt / IPI code
RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h
RISC-V: add a definition for the SIE SEIE bit
RISC-V: implement low-level interrupt handling
irqchip: add a SiFive PLIC driver
Jim Wilson (1):
RISC-V: Don't increment sepc after breakpoint.
Palmer Dabbelt (5):
RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building the vDSO
RISC-V: Add early printk support via the SBI console
clocksource: new RISC-V SBI timer driver
dt-bindings: interrupt-controller: RISC-V local interrupt controller
dt-bindings: interrupt-controller: SiFive Plaform Level Interrupt Controller
Zong Li (1):
RISC-V: Add the directive for alignment of stvec's value
.../interrupt-controller/riscv,cpu-intc.txt | 44 ++++
.../interrupt-controller/sifive,plic-1.0.0.txt | 58 +++++
arch/riscv/Makefile | 3 +
arch/riscv/configs/defconfig | 1 +
arch/riscv/include/asm/csr.h | 1 +
arch/riscv/include/asm/irq.h | 5 +-
arch/riscv/include/asm/perf_event.h | 1 +
arch/riscv/include/asm/smp.h | 6 -
arch/riscv/kernel/entry.S | 4 +-
arch/riscv/kernel/head.S | 2 +
arch/riscv/kernel/irq.c | 55 ++++-
arch/riscv/kernel/perf_event.c | 1 -
arch/riscv/kernel/setup.c | 27 +++
arch/riscv/kernel/smp.c | 6 +-
arch/riscv/kernel/smpboot.c | 1 -
arch/riscv/kernel/time.c | 30 +--
arch/riscv/kernel/traps.c | 1 -
arch/riscv/kernel/vdso/Makefile | 4 +-
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/tishift.S | 42 ++++
drivers/clocksource/Kconfig | 11 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/riscv_timer.c | 105 +++++++++
drivers/irqchip/Kconfig | 12 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-sifive-plic.c | 260 +++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
27 files changed, 625 insertions(+), 59 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt
create mode 100644 arch/riscv/lib/tishift.S
create mode 100644 drivers/clocksource/riscv_timer.c
create mode 100644 drivers/irqchip/irq-sifive-plic.c
on using it as the basis of a riscv-linux-4.18 branch that consists of only
backports from the upstream kernel, which should make the RISC-V Linux
ecosystem a whole lot more stable.
I'm planning on submitting another PR with at least the icache flushing fixes
in it next week.
This is availiable as riscv-for-linus-4.19-mw0, or as riscv-linux-4.18 on
github. I've gone and marked that branch as rebase-proof under the speculation
that the PR gets merged, at which point riscv-linux-4.18 will be officially
rebase proof.
Thanks to everyone who helped out!
Here's the PR:
The following changes since commit 94710cac0ef4ee177a63b5227664b38c95bbf703:
Linux 4.18 (2018-08-12 13:41:04 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git tags/riscv-for-linus-4.19-mw0
for you to fetch changes up to 627672cf431b0379c07cc8d146f907cda6797222:
dt-bindings: interrupt-controller: SiFive Plaform Level Interrupt Controller (2018-08-13 09:39:11 -0700)
----------------------------------------------------------------
RISC-V Updates for the 4.19 Merge Window
This tag contains some major improvements to the RISC-V port, including
the necessary interrupt controller and timer support to actually make it
to userspace. Support for three devices has been added:
* Support for the ISA-mandated timers on RISC-V systems.
* Support for the ISA-mandated first-level interrupt controller on
RISC-V systems, which is handled as part of our core arch code because
it's very small and tightly tied to the ISA.
* Support for SiFive's platform-level interrupt controller, which talks
to the actual devices.
In addition to these new devices, there are a handful of cleanups all
over the RISC-V tree:
* Build fixes for various configurations
* A fix to the vDSO build's makefile so it respects CFLAGS.
* The addition of __lshrti3, a libgcc derived function necessary for
some 32-bit configurations.
* !SMP && PERF_EVENTS
* Cleanups to the arch code to remove the remnants of old versions of
the drivers that were just properly submitted.
* Some dead code from the timer driver, most of which wasn't ever
even compiled.
* Cleanups of some interrupt #defines, which are now local to the
interrupt handling code.
* Fixes to ptrace(), which while not being sufficient to fully make GDB
work are at least sufficient to get simple GDB tasks to work.
* Early printk support via RISC-V's architecturally mandated SBI console
device.
* A fix to our early debug trap handler to ensure it's always aligned.
These patches have all been through a fairly extensive review process,
but as this enables a whole pile of functionality (ie, userspace) I'm
confident we'll need to submit a few more patches. The only concrete
issues I know about are the sys_riscv_flush_icache patches, but as I
managed to screw those up on Friday I figured it'd be best to let them
bake another week.
This tag boots a Fedora root filesystem on QEMU's master branch for me,
and before this morning's rebase (from 4.18-rc8 to 4.18) it booted on
the HiFive Unleashed.
Thanks to Christoph Hellwig and the other guys at WD for getting the new
drivers in shape!
----------------------------------------------------------------
Alex Guo (1):
RISC-V: implement __lshrti3.
Atish Patra (1):
RISC-V: Fix !CONFIG_SMP compilation error
Christoph Hellwig (6):
RISC-V: remove timer leftovers
RISC-V: simplify software interrupt / IPI code
RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h
RISC-V: add a definition for the SIE SEIE bit
RISC-V: implement low-level interrupt handling
irqchip: add a SiFive PLIC driver
Jim Wilson (1):
RISC-V: Don't increment sepc after breakpoint.
Palmer Dabbelt (5):
RISC-V: Use KBUILD_CFLAGS instead of KCFLAGS when building the vDSO
RISC-V: Add early printk support via the SBI console
clocksource: new RISC-V SBI timer driver
dt-bindings: interrupt-controller: RISC-V local interrupt controller
dt-bindings: interrupt-controller: SiFive Plaform Level Interrupt Controller
Zong Li (1):
RISC-V: Add the directive for alignment of stvec's value
.../interrupt-controller/riscv,cpu-intc.txt | 44 ++++
.../interrupt-controller/sifive,plic-1.0.0.txt | 58 +++++
arch/riscv/Makefile | 3 +
arch/riscv/configs/defconfig | 1 +
arch/riscv/include/asm/csr.h | 1 +
arch/riscv/include/asm/irq.h | 5 +-
arch/riscv/include/asm/perf_event.h | 1 +
arch/riscv/include/asm/smp.h | 6 -
arch/riscv/kernel/entry.S | 4 +-
arch/riscv/kernel/head.S | 2 +
arch/riscv/kernel/irq.c | 55 ++++-
arch/riscv/kernel/perf_event.c | 1 -
arch/riscv/kernel/setup.c | 27 +++
arch/riscv/kernel/smp.c | 6 +-
arch/riscv/kernel/smpboot.c | 1 -
arch/riscv/kernel/time.c | 30 +--
arch/riscv/kernel/traps.c | 1 -
arch/riscv/kernel/vdso/Makefile | 4 +-
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/tishift.S | 42 ++++
drivers/clocksource/Kconfig | 11 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/riscv_timer.c | 105 +++++++++
drivers/irqchip/Kconfig | 12 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-sifive-plic.c | 260 +++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
27 files changed, 625 insertions(+), 59 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt
create mode 100644 arch/riscv/lib/tishift.S
create mode 100644 drivers/clocksource/riscv_timer.c
create mode 100644 drivers/irqchip/irq-sifive-plic.c
Karsten Merker
Aug 13, 2018, 4:53:03 PM8/13/18
to Palmer Dabbelt, Paul Walmsley, Atish Patra, Christoph Hellwig, sw-...@groups.riscv.org, linux...@lists.infradead.org
On Mon, Aug 13, 2018 at 01:12:24PM -0700, Palmer Dabbelt wrote:
> Below is the pull request I plan to submit on Wednesday morning. I'm planning
> on using it as the basis of a riscv-linux-4.18 branch that consists of only
> backports from the upstream kernel, which should make the RISC-V Linux
> ecosystem a whole lot more stable.
[...]
> Below is the pull request I plan to submit on Wednesday morning. I'm planning
> on using it as the basis of a riscv-linux-4.18 branch that consists of only
> backports from the upstream kernel, which should make the RISC-V Linux
> ecosystem a whole lot more stable.
> git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git tags/riscv-for-linus-4.19-mw0
Hello Palmer,
I've just taken a look at the pull request and I'm wondering about
the order of the compatible entries in
https://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.txt?id=627672cf431b0379c07cc8d146f907cda6797222#n48
(containing 'compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic";')
and
https://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux.git/tree/Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt?id=b67bc7cb408816b94224a74dff9868d2a38bf30c#n41
(containing 'compatible = "riscv,cpu-intc", "sifive,fu540-c000-cpu-intc";')
AIUI, the kernel always binds a driver to the first matching
compatible in the list, so if I am not mistaken, the most
specific compatible should be the first in the list, with generic
compatibles following afterwards as fallbacks. Wouldn't the
order in the above examples therefore have to be the other way
round, i.e.
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
respectively
compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
?
Regards,
Karsten
--
Gem. Par. 28 Abs. 4 Bundesdatenschutzgesetz widerspreche ich der Nutzung
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Werbung sowie der Markt- oder Meinungsforschung.
Palmer Dabbelt
Aug 13, 2018, 7:15:02 PM8/13/18
to mer...@debian.org, Paul Walmsley, Atish Patra, Christoph Hellwig, sw-...@groups.riscv.org, linux...@lists.infradead.org
are doing. Do you want to submit a fixup patch or do you want me to?
>
> Regards,
> Karsten
> --
> Gem. Par. 28 Abs. 4 Bundesdatenschutzgesetz widerspreche ich der Nutzung
> sowie der Weitergabe meiner personenbezogenen Daten für Zwecke der
> Werbung sowie der Markt- oder Meinungsforschung.
>
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Karsten Merker
Aug 14, 2018, 1:46:02 AM8/14/18
to Palmer Dabbelt, mer...@debian.org, Paul Walmsley, Atish Patra, Christoph Hellwig, sw-...@groups.riscv.org, linux...@lists.infradead.org
I think it is easier and faster if you do that.
sungwo...@gmail.com
Aug 16, 2018, 3:00:15 PM8/16/18
to RISC-V SW Dev, pal...@sifive.com, mer...@debian.org, paul.w...@sifive.com, Atish...@wdc.com, h...@infradead.org, linux...@lists.infradead.org
Hello Pallmer.
I am newbie on this google groups.
I have some question about linux-riscv.
1. Where is our offical linux-riscv kernel source site?
Is it
or
2. If I want to send some patch file, where to send it?
Thank you
2018년 8월 14일 화요일 오후 2시 46분 2초 UTC+9, Karsten Merker 님의 말:
atish patra
Aug 16, 2018, 3:47:43 PM8/16/18
to sungwo...@gmail.com, RISC-V SW Dev, Palmer Dabbelt, mer...@debian.org, paul.w...@sifive.com, Atish...@wdc.com, h...@infradead.org, linux...@lists.infradead.org
On Thu, Aug 16, 2018 at 12:00 PM <sungwo...@gmail.com> wrote:
Hello Pallmer.I am newbie on this google groups.I have some question about linux-riscv.1. Where is our offical linux-riscv kernel source site?Is it
If you are using qemu, stick to the above git.kernel.org. The latest PR should work in qemu.
This also contains few out-of-tree sifive drivers which is needed for HighFive Unleashed board.
2. If I want to send some patch file, where to send it?
You should send it to linux...@lists.infradead.org
The archive is at
http://lists.infradead.org/pipermail/linux-riscv/
The archive is at
http://lists.infradead.org/pipermail/linux-riscv/
Regards,
Atish
Atish
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Regards,
Atish
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