Interrupt Delegation Confusions

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Chongfeng Hu

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Dec 8, 2021, 12:47:44 AM12/8/21
to RISC-V SW Dev
Hi,

Per risc-v privileged spec:

mideleg holds trap delegation bits for individual interrupts, with the layout of bits matching those in the mip register:

WPRI MEIP WPRI SEIP UEIP MTIP WPRI STIP UTIP MSIP WPRI SSIP USIP

Traps never transition from a more-privileged mode to a less-privileged mode. For example, if M-mode has delegated illegal instruction exceptions to S-mode, and M-mode software later executes an illegal instruction, the trap is taken in M-mode, rather than being delegated to S-mode.

What's the rationale to support delegating M-mode interrupts in mideleg? Wouldn't it be a moot point delegating e.g., M-mode external interrupts to S mode, since if it's an M-mode interrupt, only M-mode can handle it? I do notice that the mideleg register is WARL, and indeed Qemu always hard-wires the M-mode interrupt delegation bits in mideleg to 0. Would real hardware behave the same way?

Also, could someone clearly define what is an M-mode interrupt, and what is an M-mode exception? My understanding is: M-mode exception is a synchronous event that occurs when the hart happens to be executing in M-mode; whereas an M-mode interrupt doesn't necessarily mean that the hart is executing in M-mode when the event happens, it's how the PLIC is programmed to trigger an M-mode interrupt for a given event (the PLIC could alternatively be configured to trigger an S-mode interrupt instead for the same event), or for the built-in timer, it's always hard-wired to trigger M-mode interrupt, and so the mode of an interrupt is independent of the mode the hart is executing in when the event occurs. Is this understanding correct?

Regards,
Chongfeng

Andrew Waterman

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Dec 8, 2021, 2:15:48 PM12/8/21
to Chongfeng Hu, RISC-V SW Dev
On Tue, Dec 7, 2021 at 9:47 PM Chongfeng Hu <chongf...@gmail.com> wrote:
Hi,

Per risc-v privileged spec:

mideleg holds trap delegation bits for individual interrupts, with the layout of bits matching those in the mip register:

WPRI MEIP WPRI SEIP UEIP MTIP WPRI STIP UTIP MSIP WPRI SSIP USIP

Traps never transition from a more-privileged mode to a less-privileged mode. For example, if M-mode has delegated illegal instruction exceptions to S-mode, and M-mode software later executes an illegal instruction, the trap is taken in M-mode, rather than being delegated to S-mode.

What's the rationale to support delegating M-mode interrupts in mideleg? Wouldn't it be a moot point delegating e.g., M-mode external interrupts to S mode, since if it's an M-mode interrupt, only M-mode can handle it? I do notice that the mideleg register is WARL, and indeed Qemu always hard-wires the M-mode interrupt delegation bits in mideleg to 0. Would real hardware behave the same way?

Yeah, you’ve effectively answered your own question: implementations generally hard-wire those bits to 0, and so there is no support in practice for delegating those interrupts.


Also, could someone clearly define what is an M-mode interrupt, and what is an M-mode exception? My understanding is: M-mode exception is a synchronous event that occurs when the hart happens to be executing in M-mode; whereas an M-mode interrupt doesn't necessarily mean that the hart is executing in M-mode when the event happens, it's how the PLIC is programmed to trigger an M-mode interrupt for a given event (the PLIC could alternatively be configured to trigger an S-mode interrupt instead for the same event), or for the built-in timer, it's always hard-wired to trigger M-mode interrupt, and so the mode of an interrupt is independent of the mode the hart is executing in when the event occurs. Is this understanding correct?

Indeed.


Regards,
Chongfeng








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Chongfeng Hu

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Dec 8, 2021, 3:20:44 PM12/8/21
to RISC-V SW Dev, andrew, RISC-V SW Dev, Chongfeng Hu
Thanks for the clarifications!

These details are not explicit in the spec, and I had to come up with these speculations based on discussions on the web. Wish that these behaviors can be explicitly described in future spec revisions.

Also, it looks like the SiFive Interrupt Cookbook's description (https://starfivetech.com/uploads/sifive-interrupt-cookbook-v1p2.pdf) is incoherent. It says the following:

Timer interrupts always trap to Machine mode, unless delegated to Supervisor mode using the mideleg register.

From our discussions, we know that timer interrupts will always trap to M-mode, regardless of delegation settings in mideleg, because M-mode interrupts can only be handled by an M-mode trap handler, correct?

scott....@arilinc.com

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Dec 8, 2021, 8:33:02 PM12/8/21
to RISC-V SW Dev, chongf...@gmail.com, RISC-V SW Dev
Perhaps they count STIP as a "timer interrupt"? Even though it's exclusively controlled by M-mode software and not by any interrupt pin.
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