Per risc-v privileged spec:
mideleg holds trap delegation bits for individual interrupts, with the layout of bits matching those in the mip register:
WPRI MEIP WPRI SEIP UEIP MTIP WPRI STIP UTIP MSIP WPRI SSIP USIP
Traps never transition from a more-privileged mode to a less-privileged mode. For example, if M-mode has delegated illegal instruction exceptions to S-mode, and M-mode software later executes an illegal instruction, the trap is taken in M-mode, rather than being delegated to S-mode.
What's the rationale to support delegating M-mode interrupts in mideleg? Wouldn't it be a moot point delegating e.g., M-mode external interrupts to S mode, since if it's an M-mode interrupt, only M-mode can handle it? I do notice that the mideleg register is WARL, and indeed Qemu always hard-wires the M-mode interrupt delegation bits in mideleg to 0. Would real hardware behave the same way?
Also, could someone clearly define what is an M-mode interrupt, and what is an M-mode exception? My understanding is: M-mode exception is a synchronous event that occurs when the hart happens to be executing in M-mode; whereas an M-mode interrupt doesn't necessarily mean that the hart is executing in M-mode when the event happens, it's how the PLIC is programmed to trigger an M-mode interrupt for a given event (the PLIC could alternatively be configured to trigger an S-mode interrupt instead for the same event), or for the built-in timer, it's always hard-wired to trigger M-mode interrupt, and so the mode of an interrupt is independent of the mode the hart is executing in when the event occurs. Is this understanding correct?