Learning to design/implement Superscalar OOO processor.

[ra riscv]

Hoping to get some input from here.

I am looking for projects/exercises to gain deeper insights & understanding in practical aspects of designing superscalar out-of-order processor.

I have spent last 1 year in understanding various aspects of computer architecture starting from courses that teach basics for eg. 6.004x(MIT), nandtotetris & Prof Mutlu's Digital Design course(and many more) and finally moving to courses that focuses on computer architecture in general(6.823 MIT, CS152/252 Berkeley, 6.375 MIT etc).

I have also done computer architecture courses offered by Prof Wentzlaff and Prof Mutlu. During the journey, I have implemented a basic 5 stage in order RV32I architecture in verilog and bluespec.

One thing that is lacking in many of the more advanced courses is the implementation part when it comes to superscalar/out of order processors. Its probably available in the on campus offering, however not to the general public. That is the missing link for me.

I guess what i am trying to say here is that i understand(i hope) the theoretical aspect ,but i want to get my hands dirty via core implementation. Being an amateur in the field, it would be good to go through guided examples though. Thats'why BOOM/RSD etc becomes too complex, if you try to learn from them.

I am looking for something like https://dl.acm.org/doi/abs/10.1145/1275521.1275529, where Prof. Hoe only teaches what is meant to gain deeper insights. However the article is 17 years old and exercises not maintained. I hope i was able to convey, what i am looking for. I hope i will get some good takeaways.

[Bruce Hoult]

I think this is just a very advanced topic. Of course there are some university lectures covering it in simple terms, and some things in text books such as Hennessy and Patterson, but the real details are big secrets at companies such as Intel, AMD, IBM.

Don't forget BOOM was a research project in the context of a university.

ARM with all its long experience only just shipped its first OoO CPU, the Cortex-A57 in 2014. It was not really so great and the second version, the A72 in 2016, was much better.

In October SiFive announced their OoO RISC-V 8-series core and I suppose you could expect to see it sometime next year. You can be pretty sure they had a sizable team working on it for quite a long time.

There is an project to create an open source (or, as they say, Libre) OoO RISC-V core based on a modernized version of the well-documented principles behind the 1965 CDC 6600. They say they will tape-out in October, but you know how these things go. Also it is no longer just RISC-V -- apparently it is planned to run both RISC-V user-mode code and POWER user mode and privileged code. And custom GPU opcodes as well. A daunting project to say the least.

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[ra riscv]

Thanks for the response Bruce.

I understand your point completely that the complexity of a general purpose/ full fledged processor will be humongous. But that's not what i am looking for. I am looking for a starting point which will well equip me with the basics, so that i can explore other micro-architectural possibilities.(Just like the link i mentioned in the post). I am not looking to understand today's processors which offer so much performance. They have been optimized to the level at which they are now in say 20-25 years.

I know that BOOM started as a research project. But it has been modified to an extent(of course to improve its performance so as to compete with today's processors.Kudos to Chris in doing a great job :) ), that it has become too difficult to learn from it.(and I dont think that its even meant for this purpose also).

I think Prof. Joe's approach was remarkable at that time(2003). Can we even attempt to do something like that now?