New RISC-V virtual platform

[Marius Monton]

Hello, 

I want to announce another RISC-.V simulator. 

It is a cycle-accurate simulator simulating a RV32CAM (ISA Version 2.2). It is intended to be a easy to understand and use simulator for teaching purposes. 

The simulator includes memory, timers and a trace peripheral (similar to ARM's ITM) and it can execute gcc binaries out-of-the box. 

The entire code is in SystemC + TLM (C++ based) and is extensible in many ways.

The entire project is dockerized to ease the use.

Although performance is not a must, currently its performances is 3.000.000 instructions / sec in a Intel Core i7-8...@1.8Ghz.

You can find it at https://github.com/mariusmm/RISC-V-TLM

Regards,

Màrius

[Ashraful Islam]

Great works. 

Do you have plans for vector extension support in future.

Thank you.

Ashraful 

On Dec 16, 2019, at 17:25, Marius Monton <marius...@gmail.com> wrote:



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[Marius Monton]

Thank you,

My intention is to enhance the simulator and include other extensions with final degree projects from students. Maybe next semester I have some working on that.

Bests,

Màrius

--

Màrius

[kr...@berkeley.edu]

Hi Marius,

Thanks for working on RISC-V!

One detail is that there is a canonical ordering of ISA extension
names, so the ISA string should be quoted as RV32IMAC. Retaining the
same ordering helps everyone quickly determine what's being
implemented, and some letters depend on what's earlier in the string.

Krste