Age is Just a Number: Meet 13-Year-Old Ahtesham, Who Built His Own RISC-V CPU Core

[Anagha Ghosh]

When Steve Hoover and I launched the Microprocessor for You in Thirty Hours (MYTH) Workshop, our goal was to inspire students to explore logic design earlier in their academic journeys—perhaps as college freshmen or sophomores. But then came Ahtesham Ahmed, a Class 7 student from APS Jabalpur, who redefined what’s possible with sheer determination.

At just 13 years old, Ahtesham joined our workshop, absorbed the fundamentals of RISC-V ISA, developed circuit design skills, and built a pipelined calculator—all within 10 days. While many participants pause after the workshop concludes, Ahtesham persisted. Balancing school and late-night coding sessions, he pushed forward long after the final session ended.

What makes his achievement remarkable:

• Mastered RISC-V tools and circuit design in days.

• Built a non-pipelined CPU—an impressive milestone.

• Tackled Module 5, designing a 5-stage pipelined CPU with hazard handling, a challenge even for advanced learners.

Ahtesham’s story isn’t just technical brilliance - it’s about curiosity, grit, and refusing to let age define capability. While many his age might shy away from complex problem-solving, he embraced debugging pipelines and logic gates. His GitHub repo (below) is a testament to his dedication.

To anyone hesitating because they feel too young, inexperienced, or not ready: Ahtesham proves that passion and persistence outweigh labels. The future of innovation belongs to those who start today, no matter their starting point.

A huge congratulations to Ahtesham - we’re excited to see where his journey leads next! To all aspiring creators: What bold project will you pursue? Let’s celebrate those who chase ambitious goals, regardless of age or circumstance.

Explore Ahtesham’s RISC-V core here: https://github.com/Ahtesham18112011/RISCV_MYTH

Here's the RISC-V Based MYTH course link: https://www.vlsisystemdesign.com/riscv-based-myth/