VSD/Redwood EDA RISC-V 10-week Hardware Design Program

[Anagha Ghosh]

Hi RISC-V participants,

I hope everyone had an amazing experiences in the workshop and while developing new RISC Core. We request you all to do little research in market about the revolution RISCV will bring in near future. This era is similar to the early 90's when Intel x86 was launched and people who acquired the skills to design products for this architecture today are the leaders of the top most Semiconductor Industry.

Think about Hardware Design Program, as the knowledge from Workshop is fresh and you have great chance to work with the best minds on RISCV community.

Please find the details about RISC-V internships/Hardware Design Program.

Attaching curriculum and fee details at bottom of this email

To know more about pricing, please drop us an email at v...@vlsisystemdesign.com

LAST DATE TO APPLY - 5th April

Below are the details

Training (Week 1/2)

Week 1/2 – RISC-V based MYTH workshop

Dates –Starts on 17th April

Description – A beginner level 5-day workshop on “RISC-V based MYTH”  (24hrs x 5days on VSD-IAT platform) [For people who have already done this, can directly enroll for program]

When we say, “beginner level”, by end of workshop you will understand RISC-V specs, RISC-V software, how to implement RISC-V basic specs using TL-Verilog and Simulate your own RISC-V core
In short, you are going to write RTL and build RISC-V core on your own

Goals to be achieved:

·        Students will be able to use RISC-V simulator for a basic C program

·        Students will understand how to debug assembly code using spike

·        Students will understand a flow about how to write test-bench which loads a C program from memory on to a basic RISC-V core written in verilog

·        Students will be able to learn digital design basics using transaction level Verilog

·        Students will be able to code entire synthesizable RISC-V core using TL-Verilog, which can be taken further for RTL2GDS

Online Hardware design program (Week 3 –  Week 10)

Doing  project is the most important milestone in Engineer’s Professional career. Any individual getting to read for the Industry Career needs to embed few basic skills of project purpose understanding, planning, implementation, documentation, and execution stages. The below project is divided in different stages wherein student will undergo the same process followed in any corporate industry.

Week 3 - 10 – Project

Dates – As per internship dates

Project Execution Phases (VSD – 5stage process)

Understanding- Stage 1 – Week 3 – Application/Project allocation and Literature Survey - What to do, why to do & How to do?

Planning and Implementation- Stage 2 – Week 4 & 5 – Application/Project algorithm development and implementation

Documentations-Stage 3 – Week 6 – Report Submission standard VSD format which is like IEEE publication and many of the world-famous VLSI Journals.

Execution- Stage 4 – Week 7, 8, 9 – Algorithm/Project final deployment/testing

Milestone -Stage 5 – Week 10 – Final documentation, report generation format

 

Project Areas (Students will be allotted project in one of below areas based on their performance in 2-weeks training):

1.   Circuit Visualization for simulations using JavaScript and testing using Verilog/System Verilog/TL-Verilog

2.   WARP-V - Many-Core in the Cloud which includes maturity of hardware functionality, implementation characterization & optimization, and developing test programs in RISC-V assembly language program  

3.   Block-Based Circuit Design to enable 12–15-year-old programmers to develop RISC-V core using TL-verilog

4.   Implementing other ISAs in WARP-V

5.   Test and implement AES, FFT, RSA, FIR using TLV -> Synth (standalone fpga/1st-Class)

6.   Code basic SPICE simulator to generate Id-Vds NMOS Drain current modelling and execute in RISC-V MYTH core

All the best and happy learning