Learning RISC-V architecture from scratch

[Surendra Allam]

Hello all,

       Surendra here, I am new to this architecture, want to learn from scratch, please suggest me the resources to learn. I have only little knowledge regrading other architectures(RISC, CISC, Linux) as well,

Thanks in advance.

Best regards,

Surendra Allam.

[Edgar Handy]

Hello Surendra,

I have some resources that can be used to learn RISC-V from scratch, but may I know which area of RISC-V that you are interested in, so I can think of some suggestions?

For example, maybe the software or microarchitecture or basic understanding of the ISA etc etc or maybe everything step by step? :)

Regards,

Edgar Handy

[Surendra Allam]

Hello Edgar,

     Thank you s much for early reply, I would be interested to learn everything step by step, It will be very helpful  if you can share related resources.

Best regards,

Surendra Allam.

[Edgar Handy]

Hello Surendra,

I will try my best to give you some resources that I know, but this might be a bit long. (Also I suggest you read through first before start clicking the links to avoid confusion :) )

Do you feel comfortable reading the long official user and privilege manual that is released by RISC-V foundation?

If you do, the following link has 3 specifications that define RISC-V standard; Unprivileged Specification, Privileged Specification, and Debug Specification.

https://riscv.org/specifications/

Unprivileged spec defines RISC-V machine instructions behavior that are used by software without "special" permission in the processor (as the name says unprivileged). So I suggest to start from reading Unprivileged spec.

Later on, you might want to read the privileged spec for understanding instructions that control some behaviors of the processor such as external interrupt, timer, etc which usually requires special permission.

Next, if you want to learn basic microarchitecture of RISC-V, I wrote a RISC-V architecture tutorial to implement RISC-V base instructions datapath that you can find in the following link (it is not polished yet and I'm open for any feedback):

https://www.symmathics.com/index.php/risc-v-processor-component/

The tutorial is updated periodically when I have time to write :) but the basic architecture tutorial is done. They are very basic, just single cycle.

Now, if you feel what I wrote suck a lot, you should take a look at this book by David A. Patterson and John L. Hennessy: http://home.ustc.edu.cn/~louwenqi/reference_books_tools/Computer%20Organization%20and%20Design%20RISC-V%20edition.pdf

You might be familiar with these authors :)

If you want to implement a minimalist programmable RISC-V CPU and have Arty A7-35T FPGA board, I have Verilog codes that I wrote for students here in Japan (Ritsumeikan University) and toolchain to program + debug the software on it.

The code and explanation can be found in the following link: https://www.symmathics.com/index.php/symmathics-zero-risc-v-lite-about/

Arty A7-35T is expensive, so you can also use simulator (e.g. Verilator, Icarus Verilog, etc) to simulate the Verilog code if you want. However, the toolchain is designed for the board.

There are a lot of much better RISC-V softcore implementation you can find but most of them are highly complex architecturally and/or they are usually not supported by dedicated toolchains for programming and debugging.

I feel it is nice to learn and implement a simple and programmable one first :) (without having to worry about multicore, out-of-order execution, superscalar, cache coherrency, etc etc etc)

If you don't care about implementing RISC-V in silicon, emulator is always a good tool to learn the software :)

I haven't used them but these are popular ones: 

• Spike RISC-V ISA Simulator: https://github.com/riscv/riscv-isa-sim
• RISCVEMU: https://riscv.org/software-tools/riscvemu/
  
• RISCV QEMU: https://wiki.qemu.org/Documentation/Platforms/RISCV
  

Last but not least, if you are crazy about creating RISC-V CPU with a lot of configurations take a look at Rocket Chip: https://bar.eecs.berkeley.edu/projects/rocket_chip.html

It helps you generate multicore RISC-V with a lot variants (cache, memory controller, etc) for simulation or FPGA.

There are more resources out there, but I feel these are a lot already to keep you busy for a while.

My explanation might not be the best, but I hope it helps you. If you have further question, please feel free to send bunch of questions because I'm also learning from being asked :)

Regards,

Edgar

[Surendra Allam]

Thank you so much Edgar, will go through it and get back to you if any help required.

Best regards,

Surendra Allam.

[Edgar Handy]

Glad to help! :)

Regards,

Edgar

[Saif Abrar]

Hello Edgar,
Really appreciate your detailed info on RISC-V learning resources!

Regards,
Saif Abrar
IBM

[Edgar Handy]

Hello Saif,

Thank you for the comment! 

I'm always open for feedback/critics for the resources that I provide :)

Regards,

Edgar

[Neshitha Nichanametla]

Hey Edgar,
the site that you provided for your tutorial of risc v architechture implementation,we are unale to reach that site
could you please provide anyother soure.
Thankyou,
N.Neshitha