RISC-V Implementation in C++

[Awais Ahmed]

Hi,

       Is there anyone to who has implemented RISC-V (5 stage pipelined architecture) in C++  for simulation purpose? I have to implement RISC-V architecture in C++ so i have no idea how to start it. If it possible then please share your code.

Regards,

Awais Ahmed  

[Stef O'Rear]

Are you looking for something like http://gem5.org/ ?

-s

[Christopher Batten]

Hi Awais,

As Stef says, you might want to take a look at gem5. gem5 includes both simple in-order microarchitectural timing models as well as more complex out-of-order microarchitectural timing models. It may or may not be suitable for teaching depending on the scope of what you are trying to achieve.

Alec Roelke and Mircea Stan at the University of Virginia took the lead on the initial RISC-V gem5 port with support for single-threaded syscall emulation. This should currently be available in the master branch for gem5:

https://gem5.googlesource.com/public/gem5/+/master/src/arch/riscv

My own research group at Cornell has been taking the lead on the RISC-V gem5 port with support for multi-threaded syscall emulation. We are in the process of upstreaming our patches and going through the corresponding code review.

Best,
Chris

----------------------

Christopher F. Batten

Associate Professor @ ECE, Cornell University
Visiting Scholar @ The Computer Laboratory, University of Cambridge
Visiting Fellow @ Clare Hall, University of Cambridge

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[Jeremy Bennett]

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Hi Awais,

Here is another approach which may be of interest. Depends what you
want to use your simulation for.

We generate a cycle accurate C++ model from the Verilog of the PULP
project's RI5CY core using Verilator (although I think they have a 4
stage pipeline). This model is used for nightly GNU tool chain
regression testing. It runs at around 400KHz on a modern laptop.

https://github.com/embecosm/ri5cy

You will need a very up-to-date version of verilator.

I'm not sure the instructions in the README are correct. You might
need to run "make" just from the verilator-model directory. I'm OoO,
so I've copied in my colleague, Graham Markall who may be able to
clarify this.

There is a simple testbench to exercise the model. There is a separate
repository with a GDB server to wrap around the model so you can
connect from GDB to load and run programs.

HTH,


Jeremy

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[graham....@embecosm.com]

We submitted the Verilator model back to the upstream pulp-platform project, so it would be best to use that version instead, which will have all the latest fixes and changes to the core - to use it, see the README in the upstream repo:  https://github.com/pulp-platform/riscv/tree/master/verilator-model

The testbench demonstrates how to put a program in memory and step the CPU, and to read debug registers, so you needn't use a gdbserver etc. just for trying it out and running simple programs.

Best regards,

Graham.

[Peiqi Chen]

Hi,

If you have implementation about RISC-V (5 stage pipeline version), mind sharing with me? Just need to do it and have no idea how to implement 5 stage core:/ Just done with single core.

Thanks!
Peiqi