[announcement] WebRISC-V 1.7 relased - A RISC-V 64-bit (RV64IM) web-based educational simulator with pipeline

[Roberto Giorgi]

Good Morning All,

we'd like to announce of the release (1.7) of an improved version of the WebRISC-V simulator that you may already know since WCAE-2019:

-- here is the link for the paper: https://dl.acm.org/citation.cfm?id=3338894

-- here is the link to use the simulator: http://www.dii.unisi.it/~giorgi/WebRISC-V

As far as we know, it's the only simulator worldwide that permits immediate testing (including pipeline simulation) of the RV64IM assembly programs, which are proposed in the Patterson-Hennessy book, RISC-V edition:

-- https://www.elsevier.com/books/computer-organization-and-design-risc-v-edition/patterson/978-0-12-812275-4

In that sense, at this time this is probably the only RISC-V 64-bit pipeline simulator, which is "RISC-V edition, Patterson-Hennessy compliant" :-) since that book is using the 64-bit ISA and we are faithfully using their pipeline design. Moreover, it is web-based (no Java)!

We believe that the simulator is now ready for a wider sharing and deployment, as it has been improved in a number of ways since last June:

- it covers now the complete RV64IM extensions (except the "fence" instruction)

- the simulator can now execute the basic system calls (ECALL instruction)

- the forwarding logic can be excluded from both the diagram and simulation

  (this in combination with a visualization of only the control- or data-path)

- the parser now accepts the basic directives ( .ascii, .space, .word, ...)

- optionally, it shows the classical pipeline diagram too, showing where the pipeline stalls with a '-'

...and several other smaller improvements. We include below some screenshots of the simulator. You are also welcome to contribute to it as the project source is open:

   https://github.com/Mariotti94/WebRISC-V

Thanks a lot for any feedback or suggestion!

Roberto Giorgi and Gianfranco Mariotti (University of Siena - Italy).

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PICTURES of WebRISC-V follow (in the web version each architectural block is "alive" and can be inspected during the execution)

* overview of the pipelined execution with detailed ISA encoding and pipeline diagram:

* pipelined RISC-V 64 bit without forwarding

  pipelined RISC-V 64 bit *with* forwarding  

*  pipelined RISC-V 64 bit control path

 * pipelined RISC-V 64 bit data path

* RISC-V RV64IM cheat sheet and built-in editor

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Roberto Giorgi, PhD
Dipartim. Ing. Informazione, Via Roma 56 c/o INGEGNERIA, 53100 Siena (Italy)
http://www.dii.unisi.it/~giorgi