Sharing my MIPS JAL/JR Flow Visualization project

[Trần Thế Hảo]

Dear RISC-V International team and ISA Dev community,

My name is Tran The Hao, a student at Ho Chi Minh City University of Transport in Vietnam. I am very interested in CPU architecture, especially MIPS and RISC-V.

I have created a small visualization demo of the MIPS JAL/JR control flow, which you can view here: https://claude.ai/public/artifacts/ea9a8c7a-d64e-4bac-84c9-ce51bf90729c. The goal of this project is to help students better understand control flow, pipeline behavior, and branch/jump instructions in a more intuitive and visual way.

I would like to share this project with the RISC-V community and kindly ask for any feedback or suggestions you may have. I am also wondering whether a similar visualization could be useful as educational material or outreach content for RISC-V, and how I might adapt or extend it in that direction.

Thank you very much for your time and consideration. I would be happy to revise or expand the project based on your comments.

Best regards,
Tran The Hao
Ho Chi Minh City University of Transport (UT-HCMC)
Ho Chi Minh City, Vietnam
Email: haot...@ut.edu.vn