Hello Taj,
I really appreciate the feedback and it is great to hear that the program functions well as a teaching tool. Which university did you teach the course at?
If what you are looking for is something like Ripes, with a graphical view that presents a single cycle (ie. the pipeline registers removed as well as the forwarding logic), then sadly this is not (yet) doable by Ripes.
The internal simulator code as well as graphical view is close to hard-coded, and given this, i do not see a way to provide a clean interface.
If what you are in need of is a single cycle simulator with a view of the registers, memory as well as nice UI, i highly recommend the Venus simulator:
http://www.kvakil.me/venus/
The lack of multiple processor views in Ripes is something which has bothered me for a while, given that having graphical views of different processors (such as the following) would likely aid in teaching, using the Patterson-Hennessy book
* Single cycle
* 2/3 stage pipeline
* 5 stage pipeline:
* Without forwarding/hazard detection
* With forwarding/hazard detection
* Branching logic in different stages
Wherein the user would be able to write their code in the assembly editor, switch to the processor tab, select which processor to simulator the code on, and see how these different implementations have different effect on execution.
I am currently working on a project which should make something like this much more feasible, but it will probably take a while before this is integrated into Ripes. However, I will keep this post update whenever improvements to Ripes are made.
Regards,
Morten