Ripes v2.2.0 has just been released: Memory mapped I/O, dual-issue processor model, and more!

[Morten Petersen]

Ripes version 2.2.0, a graphical processor simulator and assembly editor for the RISC-V ISA, has just been released.

Major new features includes:

• Support for memory mapped I/O, with a few example devices such as an LED matrix and switches.
• Two new processor models:
  • A 6-stage dual-issue processor, for illustrating a design point capable of reaching an IPC > 1
  • A 5-stage processor without forwarding
• Complete rework of the assembler/disassembler infrastructure; added more directives, expression evaluation, as well as simplifying the process of adding new ISAs to Ripes.
• Real-time plotting of cache simulation statistics.
• A bunch of UI changes as well as general performance improvements.

If this sounds interesting, I highly suggest that you check out the new release, to both benefit from the many bug fixes and new features that's been made available over the last ~year, since version 2.0.0.

Prebuilt binaries are available on the GitHub release page.

Below is an image of the new 6-stage dual-issue model in darkmode.

[Kim McMahon]

Hello Morten,

This sounds interesting! If you send me a link, I can share it on our website via our In the News. If you share social posts, I’ll re-share.

Best,

Kim

Kim McMahon

Director of Visibility & Community Engagement, RISC-V

Mobile +1 303-570-2454

k...@RISCV.org

kmcm...@linuxfoundation.org

Twitter @kamcmahon

Schedule a meeting with me!

Interested in learning about RISC-V membership? Ask me!

<ripes_6stage.png>

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[Morten Petersen]

Hi Kim,

Here's a link to the GitHub repo, which serves as a landing page for the project: https://github.com/mortbopet/Ripes

I'm unfortunately not on twitter, so i won't be able to point towards an announcement tweet.

Thank you very much!

- Morten