Ripes version 2.0.0 has been released! A graphical processor simulator for the RISC-V ISA

[Morten Petersen]

I am excited to announce the release of the first major update to Ripes, a graphical processor simulator & assembly editor for the RISC-V ISA. This update represents a complete overhaul of the simulator and visualization infrastructure as well as a revamp of the user interface.

The update aims to address many of the feature requests I've received since first announcing the Ripes simulator on the RISC-V Teach mailing list a couple of years ago.

Some of the major new features includes:

* Multiple processor models

    * Single cycle

    * 5 Stage without hazard detection/resolution and forwarding

    * 5 Stage without hazard detection/resolution

    * 5-stage Pipeline

* Reversible simulation

* Interactive visualizations

For a full list of the new major features, refer to the release notes as well as the updated introductory document.

Interested in trying out the new release? Prebuilt binaries for all major distributions are available through the GitHub Releases page.

Ripes is open source and made available through GitHub: https://github.com/mortbopet/Ripes.

- Morten Borup Petersen

[Saif Abrar]

Hello,
very nice updates!
Too Keen to try it out soon.

Regards,
Saif

[Rajesh Kumar]

I am teaching my first system course, and Ripes was a great finding. I would want the web version to develop further, like https://editor.p5js.org/ where one can program, save code, and share a link so students can do their homework and share a link --- or add a feature like classroom in https://www.onlinegdb.com/

Thanks again for making such a wonderful tool!