Why Bluespec SV is used for Risc V

[santhosh R]

Hello everyone, I am new to VLSI design and started exploring Risc V. It seems Bluespec SV is usually preferred to design Risc V Cores and I was just wondering why?

Thank you for helping in advance...

[Shivam Potdar]

Hi Santhosh, 

I am happy to see your interest in RISC-V. I believe you are looking at the processors from the Shakti group at IIT Madras or the ones like Piccolo made by Bluespec. 

RISC-V just specifies the ISA, people can implement their own architecture using any tools of their choice.

Bluespec Verilog is one such tool, there are examples in other new (or non-Verilog/VHDL backends) like Chisel, TL-Verilog, SpinalHDL etc.

To answer the "why" in your question, Verilog/VHDL has been around for 30 years or so and people are trying to explore new methodologies to design and verify faster.

Regards

Shivam Mahesh Potdar 4th (Senior) Year BTech (Electrical and Electronics Engineering) National Institute of Technology Karnataka, Surathkal, India  mobile:  +91-9511893050 website:  shivampotdar.me LinkedIn: shivampotdar99 email:  shivamp...@gmail.com | shivam....@nitk.edu.in

On Wed, Nov 25, 2020 at 11:57 AM santhosh R <santoshram...@gmail.com> wrote:

Hello everyone, I am new to VLSI design and started exploring Risc V. It seems Bluespec SV is usually preferred to design Risc V Cores and I was just wondering why?

Thank you for helping in advance...

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[Ted Speers]

Bluespec has played an important role in the history of RISC-V.  If you go here, you’ll see some videos detailing their important role (see Arvind (MIT), G.S. Madhusudan (IIT Madras) and Rishyur Nikhil (MIT, Bluespec). 

 

There are RISC-V cores available in many languages.

 

The original RISC-V was developed at Berkeley using Chisel and is now used extensively commercially at SiFive.  To see Chisel’s growing use in academia and industry, check out https://events.linuxfoundation.org/chisel-community-conference/.

 

A RISC-V Foundation contest winning core was developed in SpinalHDL, a Scala based HDL (as is chisel). https://github.com/SpinalHDL/VexRiscv

 

Cores developed at ETH Zurich and now hosted by the Open Hardware Group have seen wide industry adoption and are available in system Verilog .. https://www.openhwgroup.org/projects/

 

Picosoc ( https://github.com/cliffordwolf/picorv32/tree/master/picosoc ) is a small RISC-V core developed in Verilog.