What happens when PLIC enables one interrupt on all processors?
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vladimir mitrofanov
Sep 14, 2021, 6:20:06 AM9/14/21
to RISC-V ISA Dev
Hi, folks. Could anyone give me an answer to what will happen when I enable an interrupt on all CPUs?
One of the CPUs runs an interrupt handler and what do others Do they run the same handler or maybe they don't require this interrupt?
Rishiyur Nikhil
Sep 14, 2021, 10:42:12 AM9/14/21
to vladimir mitrofanov, RISC-V ISA Dev
The protocol is that harts should first "claim" the interrupt from the
PLIC (see "Interrupt Claims" section of PLIC spec).
This is an atomic action on the PLIC, so even if multiple harts
attempt to claim, only one will succeed. Presumably that hart is the
one that will then service the interrupt.
Nikhil
PLIC (see "Interrupt Claims" section of PLIC spec).
This is an atomic action on the PLIC, so even if multiple harts
attempt to claim, only one will succeed. Presumably that hart is the
one that will then service the interrupt.
Nikhil
On Tue, Sep 14, 2021 at 6:20 AM vladimir mitrofanov <vladimirmi...@gmail.com> wrote:
Hi, folks. Could anyone give me an answer to what will happen when I enable an interrupt on all CPUs?
One of the CPUs runs an interrupt handler and what do others Do they run the same handler or maybe they don't require this interrupt?
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Anup Patel
Sep 14, 2021, 11:11:41 AM9/14/21
to Rishiyur Nikhil, vladimir mitrofanov, RISC-V ISA Dev
On Tue, Sep 14, 2021 at 8:12 PM Rishiyur Nikhil <nik...@bluespec.com> wrote:
>
> The protocol is that harts should first "claim" the interrupt from the
> PLIC (see "Interrupt Claims" section of PLIC spec).
>
> This is an atomic action on the PLIC, so even if multiple harts
> attempt to claim, only one will succeed. Presumably that hart is the
> one that will then service the interrupt.
Yes, this is correct.
>
> The protocol is that harts should first "claim" the interrupt from the
> PLIC (see "Interrupt Claims" section of PLIC spec).
>
> This is an atomic action on the PLIC, so even if multiple harts
> attempt to claim, only one will succeed. Presumably that hart is the
> one that will then service the interrupt.
This also means if we had N harts with IRQx enabled then all
N harts attempt to claim IRQx but only one succeeds whereas
other N-1 harts would have wasted CPU cycles in failed attempt
to claim IRQx. The Linux PLIC driver tries ensures that IRQx
is enabled only for one of the harts so that other harts don't
waste CPU cycles.
Regards,
Anup
>
> Nikhil
>
> On Tue, Sep 14, 2021 at 6:20 AM vladimir mitrofanov <vladimirmi...@gmail.com> wrote:
>>
>>
>> Hi, folks. Could anyone give me an answer to what will happen when I enable an interrupt on all CPUs?
>> One of the CPUs runs an interrupt handler and what do others Do they run the same handler or maybe they don't require this interrupt?
>>
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>> You received this message because you are subscribed to the Google Groups "RISC-V ISA Dev" group.
>> To unsubscribe from this group and stop receiving emails from it, send an email to isa-dev+u...@groups.riscv.org.
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>
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